From patchwork Thu May 15 00:32:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 4178801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 82F95BFF02 for ; Thu, 15 May 2014 00:36:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B638F20306 for ; Thu, 15 May 2014 00:36:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E13DD202EB for ; Thu, 15 May 2014 00:36:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WkjcP-0005Er-EF; Thu, 15 May 2014 00:33:53 +0000 Received: from mail-ve0-f202.google.com ([209.85.128.202]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wkjc6-00056U-8P for linux-arm-kernel@lists.infradead.org; Thu, 15 May 2014 00:33:36 +0000 Received: by mail-ve0-f202.google.com with SMTP id pa12so74603veb.3 for ; Wed, 14 May 2014 17:33:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=r5lzirf/bGZo7DN0eJ6OVmBBdY0cTa8O6UUdCyjaMz4=; b=e5TQzSbO0zAc2+5PDFV9GpYqkkrAm2MVxqNVwQuWJKj1L3vtXvTNUci6Kv54W3zeDu jxpXngQuwiXb6jxHKrBjPvETKpON70waPvqE/VJlYi4psNdiNDcJ4kPgEI5Iu1O6tAGE ZO7zAjvNFLJ5GM6A580NLMk1B/Pf+2K6sDwpq5pY3cXlv95JHRgrKEmIgOYH5TvitBFL H6WnRxv7oI1xgVKiPQIkfe4OXVIHbtJ9otStqZ73k/JDcF5fe8aA4PUvQIVdffOxloUI 1oJn77BTXPh7V+KXiqnmt1POaQSaKncdF3a5VEGQzQ9ixbbCCCz1LwlIpv8f3Mk+6u3z yWrA== X-Gm-Message-State: ALoCoQkow6SjMkWkYXC0FZcd7kvMHDozOb+Km8s43FCp98GzeHhYpmVo3HypwcsVoo85OnwXYZfh X-Received: by 10.236.87.73 with SMTP id x49mr2993503yhe.30.1400113991238; Wed, 14 May 2014 17:33:11 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id a44si166299yhb.6.2014.05.14.17.33.11 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 May 2014 17:33:11 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 0C23B31C1F8; Wed, 14 May 2014 17:33:11 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id C25D52206A7; Wed, 14 May 2014 17:33:10 -0700 (PDT) From: Andrew Bresticker To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org Subject: [RFC PATCH 01/10] clk: tegra: Enable hardware control of PLLE Date: Wed, 14 May 2014 17:32:57 -0700 Message-Id: <1400113986-339-2-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a In-Reply-To: <1400113986-339-1-git-send-email-abrestic@chromium.org> References: <1400113986-339-1-git-send-email-abrestic@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140514_173334_383904_78924EC3 X-CRM114-Status: GOOD ( 11.50 ) X-Spam-Score: -1.4 (-) Cc: Mark Rutland , Prashant Gaikwad , Russell King , Mathias Nyman , Pawel Moll , Stephen Warren , Andrew Bresticker , Greg Kroah-Hartman , Peter De Schrijver , Ian Campbell , Jim Lin , Kishon Vijay Abraham I , Rob Herring , Thierry Reding , Randy Dunlap , Kumar Gala , Grant Likely , Mike Turquette X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jim Lin Enable hardware control of PLLE spread-spectrum, IDDQ, and enable controls when enabling PLLE. The hardware (e.g. XUSB) using PLLE will use these controls for power-saving optimizations. Signed-off-by: Jim Lin Signed-off-by: Andrew Bresticker --- drivers/clk/tegra/clk-pll.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 0d20241..84ca8b9 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -96,10 +96,20 @@ (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) #define PLLE_AUX_PLLP_SEL BIT(2) +#define PLLE_AUX_USE_LOCKDET BIT(3) #define PLLE_AUX_ENABLE_SWCTL BIT(4) +#define PLLE_AUX_SS_SWCTL BIT(6) #define PLLE_AUX_SEQ_ENABLE BIT(24) +#define PLLE_AUX_SEQ_START_STATE BIT(25) #define PLLE_AUX_PLLRE_SEL BIT(28) +#define XUSBIO_PLL_CFG0 0x51c +#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) +#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) +#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) +#define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) +#define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) + #define PLLE_MISC_PLLE_PTS BIT(8) #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) @@ -1318,7 +1328,28 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); - /* TODO: enable hw control of xusb brick pll */ + /* Enable hw control of xusb brick pll */ + val = pll_readl_misc(pll); + val &= ~PLLE_MISC_IDDQ_SW_CTRL; + pll_writel_misc(val, pll); + + val = pll_readl(pll->params->aux_reg, pll); + val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE); + val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); + pll_writel(val, pll->params->aux_reg, pll); + udelay(1); + val |= PLLE_AUX_SEQ_ENABLE; + pll_writel(val, pll->params->aux_reg, pll); + + val = pll_readl(XUSBIO_PLL_CFG0, pll); + val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | + XUSBIO_PLL_CFG0_SEQ_START_STATE); + val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | + XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); + pll_writel(val, XUSBIO_PLL_CFG0, pll); + udelay(1); + val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; + pll_writel(val, XUSBIO_PLL_CFG0, pll); out: if (pll->lock)