From patchwork Fri May 16 08:41:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 4189361 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EE0589F387 for ; Fri, 16 May 2014 08:44:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 157E8202E6 for ; Fri, 16 May 2014 08:44:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B525020295 for ; Fri, 16 May 2014 08:44:08 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WlDiQ-0006tF-SA; Fri, 16 May 2014 08:42:06 +0000 Received: from mail-ee0-f54.google.com ([74.125.83.54]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WlDiA-0006gm-Tq for linux-arm-kernel@lists.infradead.org; Fri, 16 May 2014 08:41:52 +0000 Received: by mail-ee0-f54.google.com with SMTP id b57so1302267eek.27 for ; Fri, 16 May 2014 01:41:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TZSFQw4ybCGivQeMO7l7OVV8fgl0dQneev0IdTL5Gis=; b=NU6x3daFs+34IMbMKfvcQ6AZA3tjAHb+dAI5nm8FKbUHCoEtv00De4VQL+vY7ZraSu umWYqpS/9ae4ImEvqvh08o3Y/jnWkP1G/cYfnSNRtoL+30LpgesnqOBkCmLvGMhRDLNw bSxgvzhBPUBAGycQUundRrpSfnm1qqRY5NtL2g4H8ANpzo6ewkyz/0HHjOJCs148ZHzQ y+fe1YRlueHVGSXaleY2tDo1k1nAkrjIi+UIPiqcS9e7gAKFe8tVsXK0+sfZy+CcoePv Hzg3Clz7aDmfhROsuM4QtQSc9z4xIw82oFJVxCASmNj5SJeKjSbyPsEbc5bhKvM88q35 CEoA== X-Gm-Message-State: ALoCoQlbFSlUFAYCFuwB18vJokWiThNVUqV8WWOcByRoH73QMKMYDvLPoAPkajLJVId1/XJJ4M4K X-Received: by 10.14.211.133 with SMTP id w5mr20468840eeo.5.1400229687723; Fri, 16 May 2014 01:41:27 -0700 (PDT) Received: from localhost.localdomain (74.16-201-80.adsl-dyn.isp.belgacom.be. [80.201.16.74]) by mx.google.com with ESMTPSA id u1sm18410354eex.31.2014.05.16.01.41.25 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 16 May 2014 01:41:26 -0700 (PDT) From: Jean Pihet To: linux-kernel@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-arm-kernel@lists.infradead.org, Will Deacon , Jiri Olsa , Ingo Molnar , Arnaldo Carvalho de Melo Subject: [PATCH 2/4] perf tests: Introduce perf_regs_load function on ARM Date: Fri, 16 May 2014 10:41:10 +0200 Message-Id: <1400229672-16104-2-git-send-email-jean.pihet@linaro.org> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1400229672-16104-1-git-send-email-jean.pihet@linaro.org> References: <1400229672-16104-1-git-send-email-jean.pihet@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140516_014151_128120_4BC7EA82 X-CRM114-Status: GOOD ( 16.65 ) X-Spam-Score: -0.7 (/) Cc: Peter Zijlstra , Corey Ashford , Frederic Weisbecker , Paul Mackerras , Arnaldo Carvalho de Melo , David Ahern , Namhyung Kim , Jean Pihet X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introducing perf_regs_load function, which is going to be used for dwarf unwind test in following patches. It takes single argument as a pointer to the regs dump buffer and populates it with current registers values. Signed-off-by: Jean Pihet Reviewed-by: Will Deacon Cc: Corey Ashford Cc: Frederic Weisbecker Cc: Ingo Molnar Cc: Namhyung Kim Cc: Paul Mackerras Cc: Peter Zijlstra Cc: Arnaldo Carvalho de Melo Cc: David Ahern Cc: Jiri Olsa --- tools/perf/arch/arm/Makefile | 1 + tools/perf/arch/arm/include/perf_regs.h | 2 ++ tools/perf/arch/arm/tests/regs_load.S | 58 +++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 tools/perf/arch/arm/tests/regs_load.S diff --git a/tools/perf/arch/arm/Makefile b/tools/perf/arch/arm/Makefile index 67e9b3d..9b8f87e 100644 --- a/tools/perf/arch/arm/Makefile +++ b/tools/perf/arch/arm/Makefile @@ -4,4 +4,5 @@ LIB_OBJS += $(OUTPUT)arch/$(ARCH)/util/dwarf-regs.o endif ifndef NO_LIBUNWIND LIB_OBJS += $(OUTPUT)arch/$(ARCH)/util/unwind-libunwind.o +LIB_OBJS += $(OUTPUT)arch/$(ARCH)/tests/regs_load.o endif diff --git a/tools/perf/arch/arm/include/perf_regs.h b/tools/perf/arch/arm/include/perf_regs.h index bcca511..33abcfa 100644 --- a/tools/perf/arch/arm/include/perf_regs.h +++ b/tools/perf/arch/arm/include/perf_regs.h @@ -5,6 +5,8 @@ #include #include +void perf_regs_load(u64 *regs); + #define PERF_REGS_MASK ((1ULL << PERF_REG_ARM_MAX) - 1) #define PERF_REG_IP PERF_REG_ARM_PC #define PERF_REG_SP PERF_REG_ARM_SP diff --git a/tools/perf/arch/arm/tests/regs_load.S b/tools/perf/arch/arm/tests/regs_load.S new file mode 100644 index 0000000..e09e983 --- /dev/null +++ b/tools/perf/arch/arm/tests/regs_load.S @@ -0,0 +1,58 @@ +#include + +#define R0 0x00 +#define R1 0x08 +#define R2 0x10 +#define R3 0x18 +#define R4 0x20 +#define R5 0x28 +#define R6 0x30 +#define R7 0x38 +#define R8 0x40 +#define R9 0x48 +#define SL 0x50 +#define FP 0x58 +#define IP 0x60 +#define SP 0x68 +#define LR 0x70 +#define PC 0x78 + +/* + * Implementation of void perf_regs_load(u64 *regs); + * + * This functions fills in the 'regs' buffer from the actual registers values, + * in the way the perf built-in unwinding test expects them: + * - the PC at the time at the call to this function. Since this function + * is called using a bl instruction, the PC value is taken from LR. + * The built-in unwinding test then unwinds the call stack from the dwarf + * information in unwind__get_entries. + * + * Notes: + * - the 8 bytes stride in the registers offsets comes from the fact + * that the registers are stored in an u64 array (u64 *regs), + * - the regs buffer needs to be zeroed before the call to this function, + * in this case using a calloc in dwarf-unwind.c. + */ + +.text +.type perf_regs_load,%function +ENTRY(perf_regs_load) + str r0, [r0, #R0] + str r1, [r0, #R1] + str r2, [r0, #R2] + str r3, [r0, #R3] + str r4, [r0, #R4] + str r5, [r0, #R5] + str r6, [r0, #R6] + str r7, [r0, #R7] + str r8, [r0, #R8] + str r9, [r0, #R9] + str sl, [r0, #SL] + str fp, [r0, #FP] + str ip, [r0, #IP] + str sp, [r0, #SP] + str lr, [r0, #LR] + str lr, [r0, #PC] // store pc as lr in order to skip the call + // to this function + mov pc, lr +ENDPROC(perf_regs_load)