From patchwork Tue May 20 08:45:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 4208011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 24725BEEAB for ; Tue, 20 May 2014 08:52:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A9B1C20166 for ; Tue, 20 May 2014 08:52:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BF88F2015A for ; Tue, 20 May 2014 08:52:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wmfin-00053L-Un; Tue, 20 May 2014 08:48:29 +0000 Received: from mail-bl2lp0204.outbound.protection.outlook.com ([207.46.163.204] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wmfh5-0003o2-El for linux-arm-kernel@lists.infradead.org; Tue, 20 May 2014 08:46:44 +0000 Received: from DM2PR03CA006.namprd03.prod.outlook.com (10.141.52.154) by DM2PR03MB352.namprd03.prod.outlook.com (10.141.54.24) with Microsoft SMTP Server (TLS) id 15.0.944.11; Tue, 20 May 2014 08:46:19 +0000 Received: from BN1BFFO11FD051.protection.gbl (2a01:111:f400:7c10::1:160) by DM2PR03CA006.outlook.office365.com (2a01:111:e400:2414::26) with Microsoft SMTP Server (TLS) id 15.0.944.11 via Frontend Transport; Tue, 20 May 2014 08:46:19 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD051.mail.protection.outlook.com (10.58.145.6) with Microsoft SMTP Server (TLS) id 15.0.949.9 via Frontend Transport; Tue, 20 May 2014 08:46:19 +0000 Received: from dragon.ap.freescale.net ([10.192.185.75]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s4K8je55027018; Tue, 20 May 2014 01:46:16 -0700 From: Shawn Guo To: Subject: [PATCH 15/20] ARM: imx5: reuse clock CCM mapping in pm code Date: Tue, 20 May 2014 16:45:33 +0800 Message-ID: <1400575538-21136-16-git-send-email-shawn.guo@freescale.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400575538-21136-1-git-send-email-shawn.guo@freescale.com> References: <1400575538-21136-1-git-send-email-shawn.guo@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(76176999)(77096999)(48376002)(50986999)(21056001)(47776003)(20776003)(50226001)(80022001)(93916002)(86362001)(69596002)(84676001)(88136002)(81342001)(89996001)(6806004)(81156002)(81542001)(102836001)(68736004)(87936001)(50466002)(92726001)(83322001)(33646001)(19580405001)(76482001)(62966002)(36756003)(19580395003)(4396001)(92566001)(85852003)(83072002)(97736001)(77982001)(46102001)(99396002)(64706001)(31966008)(77156001)(79102001)(44976005)(74502001)(74662001)(87286001); DIR:OUT; SFP:; SCL:1; SRVR:DM2PR03MB352; H:az84smr01.freescale.net; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 02176E2458 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140520_014643_710189_4DD04D57 X-CRM114-Status: GOOD ( 11.46 ) X-Spam-Score: -0.7 (/) Cc: Shawn Guo , Alexander Shiyan , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The imx5 pm code needs to access CCM registers. Let's remove the use of CCM static mapping in pm code by reusing the dynamic mapping created in clock code. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx51-imx53.c | 2 ++ arch/arm/mach-imx/common.h | 2 ++ arch/arm/mach-imx/pm-imx5.c | 17 +++++++++++++---- 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 4b69183..4e95865 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -133,6 +133,8 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) { int i; + imx5_pm_set_ccm_base(ccm_base); + clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 1d6cf4d..8aa198c 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -143,8 +143,10 @@ void imx6q_pm_set_ccm_base(void __iomem *base); #ifdef CONFIG_PM void imx5_pm_init(void); +void imx5_pm_set_ccm_base(void __iomem *base); #else static inline void imx5_pm_init(void) {} +static inline void imx5_pm_set_ccm_base(void __iomem *base) {} #endif #ifdef CONFIG_NEON diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c index 7dfd005..3544c25 100644 --- a/arch/arm/mach-imx/pm-imx5.c +++ b/arch/arm/mach-imx/pm-imx5.c @@ -21,8 +21,7 @@ #include "cpuidle.h" #include "hardware.h" -#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) -#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) +#define MXC_CCM_CLPCR 0x54 #define MXC_CCM_CLPCR_LPM_OFFSET 0 #define MXC_CCM_CLPCR_LPM_MASK 0x3 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 @@ -57,6 +56,13 @@ */ #define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF +static void __iomem *ccm_base; + +void __init imx5_pm_set_ccm_base(void __iomem *base) +{ + ccm_base = base; +} + /* * set cpu low power mode before WFI instruction. This function is called * mx5 because it can be used for mx51, and mx53. @@ -70,7 +76,8 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) /* always allow platform to issue a deep sleep mode request */ plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & ~(MXC_CORTEXA8_PLAT_LPC_DSM); - ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); + ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) & + ~(MXC_CCM_CLPCR_LPM_MASK); arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); @@ -108,7 +115,7 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) } __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); - __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); + __raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); @@ -188,6 +195,8 @@ static int __init imx5_pm_common_init(void) arm_pm_idle = imx5_pm_idle; + WARN_ON(!ccm_base); + /* Set the registers to the default cpu idle state. */ mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);