From patchwork Tue May 20 08:45:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 4207971 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 77480BEEAB for ; Tue, 20 May 2014 08:51:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 96C6F201BF for ; Tue, 20 May 2014 08:51:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF6BA20373 for ; Tue, 20 May 2014 08:51:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wmfi6-0004TY-8z; Tue, 20 May 2014 08:47:46 +0000 Received: from mail-bl2lp0206.outbound.protection.outlook.com ([207.46.163.206] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wmfgu-0003k7-Si for linux-arm-kernel@lists.infradead.org; Tue, 20 May 2014 08:46:33 +0000 Received: from BLUPR03CA032.namprd03.prod.outlook.com (10.141.30.25) by BLUPR03MB341.namprd03.prod.outlook.com (10.141.48.12) with Microsoft SMTP Server (TLS) id 15.0.944.11; Tue, 20 May 2014 08:46:03 +0000 Received: from BL2FFO11FD039.protection.gbl (2a01:111:f400:7c09::155) by BLUPR03CA032.outlook.office365.com (2a01:111:e400:879::25) with Microsoft SMTP Server (TLS) id 15.0.949.11 via Frontend Transport; Tue, 20 May 2014 08:46:03 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD039.mail.protection.outlook.com (10.173.161.135) with Microsoft SMTP Server (TLS) id 15.0.949.9 via Frontend Transport; Tue, 20 May 2014 08:46:03 +0000 Received: from dragon.ap.freescale.net ([10.192.185.75]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s4K8je4u027018; Tue, 20 May 2014 01:45:55 -0700 From: Shawn Guo To: Subject: [PATCH 06/20] ARM: imx5: make mx51_clocks_init() a DT call Date: Tue, 20 May 2014 16:45:24 +0800 Message-ID: <1400575538-21136-7-git-send-email-shawn.guo@freescale.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400575538-21136-1-git-send-email-shawn.guo@freescale.com> References: <1400575538-21136-1-git-send-email-shawn.guo@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(93916002)(31966008)(88136002)(46102001)(6806004)(92726001)(77156001)(92566001)(74662001)(87936001)(81156002)(62966002)(48376002)(74502001)(97736001)(84676001)(20776003)(47776003)(44976005)(19580405001)(19580395003)(69596002)(86362001)(76176999)(64706001)(68736004)(80022001)(83322001)(50986999)(102836001)(4396001)(77096999)(81542001)(83072002)(50226001)(85852003)(81342001)(99396002)(77982001)(36756003)(87286001)(50466002)(89996001)(21056001)(79102001)(76482001)(33646001); DIR:OUT; SFP:; SCL:1; SRVR:BLUPR03MB341; H:az84smr01.freescale.net; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 02176E2458 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140520_014633_076101_2A713AAE X-CRM114-Status: UNSURE ( 8.38 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) Cc: Shawn Guo , Alexander Shiyan , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since i.MX51 becomes a DT only platform, we can make mx51_clocks_init() a DT call and save function mx51_clocks_init_dt() now. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx51-imx53.c | 16 +++------------- arch/arm/mach-imx/common.h | 2 -- 2 files changed, 3 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 21d2b11..1e22d35 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -375,12 +375,10 @@ static void __init mx50_clocks_init(struct device_node *np) } CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); -int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, - unsigned long rate_ckih1, unsigned long rate_ckih2) +static void __init mx51_clocks_init(struct device_node *np) { int i; u32 val; - struct device_node *np; clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); @@ -422,12 +420,11 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, pr_err("i.MX51 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); - np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm"); clk_data.clks = clk; clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); + mx5_clocks_common_init(0, 0, 0, 0); clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2"); clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL); @@ -474,15 +471,8 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, val = readl(MXC_CCM_CLPCR); val |= 1 << 23; writel(val, MXC_CCM_CLPCR); - - return 0; -} - -static void __init mx51_clocks_init_dt(struct device_node *np) -{ - mx51_clocks_init(0, 0, 0, 0); } -CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); +CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init); static void __init mx53_clocks_init(struct device_node *np) { diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 9ab785c..cf9e9c2 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -64,8 +64,6 @@ int mx25_clocks_init(void); int mx27_clocks_init(unsigned long fref); int mx31_clocks_init(unsigned long fref); int mx35_clocks_init(void); -int mx51_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2); int mx25_clocks_init_dt(void); int mx27_clocks_init_dt(void); int mx31_clocks_init_dt(void);