From patchwork Tue May 20 08:45:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 4207961 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3C5DC9F32A for ; Tue, 20 May 2014 08:50:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B8E420364 for ; Tue, 20 May 2014 08:50:41 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6F27D201BF for ; Tue, 20 May 2014 08:50:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wmfhg-0004CJ-SM; Tue, 20 May 2014 08:47:20 +0000 Received: from mail-bn1blp0188.outbound.protection.outlook.com ([207.46.163.188] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wmfgm-0003hQ-Uu for linux-arm-kernel@lists.infradead.org; Tue, 20 May 2014 08:46:25 +0000 Received: from BY2PR03CA056.namprd03.prod.outlook.com (10.141.249.29) by BY2PR03MB347.namprd03.prod.outlook.com (10.141.139.16) with Microsoft SMTP Server (TLS) id 15.0.944.11; Tue, 20 May 2014 08:46:01 +0000 Received: from BY2FFO11FD047.protection.gbl (2a01:111:f400:7c0c::167) by BY2PR03CA056.outlook.office365.com (2a01:111:e400:2c5d::29) with Microsoft SMTP Server (TLS) id 15.0.944.11 via Frontend Transport; Tue, 20 May 2014 08:46:01 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD047.mail.protection.outlook.com (10.1.15.175) with Microsoft SMTP Server (TLS) id 15.0.939.9 via Frontend Transport; Tue, 20 May 2014 08:46:00 +0000 Received: from dragon.ap.freescale.net ([10.192.185.75]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s4K8je4v027018; Tue, 20 May 2014 01:45:57 -0700 From: Shawn Guo To: Subject: [PATCH 07/20] ARM: imx5: drop arguments from mx5_clocks_common_init() Date: Tue, 20 May 2014 16:45:25 +0800 Message-ID: <1400575538-21136-8-git-send-email-shawn.guo@freescale.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400575538-21136-1-git-send-email-shawn.guo@freescale.com> References: <1400575538-21136-1-git-send-email-shawn.guo@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(199002)(189002)(76482001)(99396002)(4396001)(64706001)(62966002)(79102001)(81342001)(87286001)(20776003)(83322001)(50986999)(84676001)(77982001)(44976005)(19580405001)(47776003)(76176999)(68736004)(69596002)(46102001)(50226001)(77096999)(19580395003)(80022001)(88136002)(97736001)(83072002)(85852003)(74662001)(31966008)(33646001)(74502001)(36756003)(81156002)(77156001)(89996001)(6806004)(81542001)(86362001)(92726001)(92566001)(21056001)(87936001)(93916002)(50466002)(102836001)(48376002); DIR:OUT; SFP:; SCL:1; SRVR:BY2PR03MB347; H:az84smr01.freescale.net; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 02176E2458 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140520_014625_220057_2BC268A7 X-CRM114-Status: UNSURE ( 8.18 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) Cc: Shawn Guo , Alexander Shiyan , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The function mx5_clocks_common_init() was created with a number of arguments to pass oscillator clock rate in non-DT boot. Since i.MX5 is DT only platform, the arguments can be dropped, and the clock rate can just be retrieved from device tree. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx51-imx53.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 1e22d35..67f686e 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -86,17 +86,15 @@ static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; static struct clk *clk[IMX5_CLK_END]; static struct clk_onecell_data clk_data; -static void __init mx5_clocks_common_init(unsigned long rate_ckil, - unsigned long rate_osc, unsigned long rate_ckih1, - unsigned long rate_ckih2) +static void __init mx5_clocks_common_init(void) { int i; clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); - clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil); - clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc); - clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); - clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); + clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); + clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); + clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); + clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0); clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); @@ -358,7 +356,7 @@ static void __init mx50_clocks_init(struct device_node *np) clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - mx5_clocks_common_init(0, 0, 0, 0); + mx5_clocks_common_init(); /* set SDHC root clock to 200MHZ*/ clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); @@ -424,7 +422,7 @@ static void __init mx51_clocks_init(struct device_node *np) clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - mx5_clocks_common_init(0, 0, 0, 0); + mx5_clocks_common_init(); clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2"); clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL); @@ -542,7 +540,7 @@ static void __init mx53_clocks_init(struct device_node *np) clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - mx5_clocks_common_init(0, 0, 0, 0); + mx5_clocks_common_init(); clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2"); clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");