From patchwork Thu May 22 15:55:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 4224161 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1BFE39F23C for ; Thu, 22 May 2014 15:58:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2090D202C8 for ; Thu, 22 May 2014 15:58:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 21D93201C0 for ; Thu, 22 May 2014 15:58:17 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WnVLi-0007of-HN; Thu, 22 May 2014 15:56:06 +0000 Received: from mail-ve0-f202.google.com ([209.85.128.202]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WnVLf-0007gW-Rd for linux-arm-kernel@lists.infradead.org; Thu, 22 May 2014 15:56:04 +0000 Received: by mail-ve0-f202.google.com with SMTP id pa12so632885veb.3 for ; Thu, 22 May 2014 08:55:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=DhDr4cxXSJLdZwgf+t9LvWQs6tSs/kYfFmVI94X6A7A=; b=jEirVYmPoBCTl5d9u93wHSou1Tcs/83Nk2qANq20dhIhuQfXURzJVxVIgUySptTCzo mVyWYh3OFxaeGFrUA9ERfIXD6O6qvKqyrPUwqYTniz63nrLZuJ3XFSDNn9GLozaeBjy/ 6JFqihWwnJhM/qgUmubBhZpo2tXmW3gWcN3FBDYr1Q3+kV664FuB0faO9BAiaXsmimGZ 0toisUpaduv1fDhM1KeI/9giJNDhpsfAEj2Hm3Fk8iOGe2CUBpvaE5a2Vm4W4E3Ku9Uz QSUz93P0HCjl6cvCNtxgC/EC90eLmC4ba6becGPuPiRNQ2nzFiuX6wUX+PfEIGI/kZKd 6fGQ== X-Gm-Message-State: ALoCoQm259M8cgvGIuZau+RKw+CGOEirqkkd4HcP/7GRI6g4k4yKlF7X/EDEShP101KrgBiL71iV X-Received: by 10.58.161.175 with SMTP id xt15mr18666242veb.19.1400774140566; Thu, 22 May 2014 08:55:40 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id c50si12996yhl.7.2014.05.22.08.55.40 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 May 2014 08:55:40 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 52FC531C1B2; Thu, 22 May 2014 08:55:40 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id F1D392209D9; Thu, 22 May 2014 08:55:39 -0700 (PDT) From: Andrew Bresticker To: Chris Ball , Ulf Hansson , Stephen Warren , Thierry Reding Subject: [PATCH v3 1/2] mmc: tegra: disable UHS modes Date: Thu, 22 May 2014 08:55:35 -0700 Message-Id: <1400774136-12396-1-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140522_085603_979730_3D998772 X-CRM114-Status: GOOD ( 13.81 ) X-Spam-Score: -1.4 (-) Cc: linux-tegra@vger.kernel.org, Andrew Bresticker , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised in SDHCI_CAPABILITIES_1. While the Tegra SDHCI controller does support these modes, they require Tegra-specific tuning and calibration routines which the driver does not support yet. Signed-off-by: Andrew Bresticker Tested-by: Stephen Warren Acked-by: Stephen Warren Signed-off-by: Ulf Hansson --- Changes from v2: - rebased on mmc-next No changes from v1 --- drivers/mmc/host/sdhci-tegra.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 9852476..4375cd4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -32,11 +32,17 @@ /* Tegra SDHOST controller vendor register definitions */ #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 +#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 +#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 +#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) +#define NVQUIRK_DISABLE_SDR50 BIT(3) +#define NVQUIRK_DISABLE_SDR104 BIT(4) +#define NVQUIRK_DISABLE_DDR50 BIT(5) struct sdhci_tegra_soc_data { const struct sdhci_pltfm_data *pdata; @@ -100,20 +106,25 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = pltfm_host->priv; const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; + u32 misc_ctrl; sdhci_reset(host, mask); if (!(mask & SDHCI_RESET_ALL)) return; + misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); /* Erratum: Enable SDHCI spec v3.00 support */ - if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) { - u32 misc_ctrl; - - misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); + if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; - sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); - } + /* Don't advertise UHS modes which aren't supported yet */ + if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) + misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; + if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) + misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; + if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) + misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; + sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); } static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) @@ -170,7 +181,9 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { static struct sdhci_tegra_soc_data soc_data_tegra30 = { .pdata = &sdhci_tegra30_pdata, - .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300, + .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | + NVQUIRK_DISABLE_SDR50 | + NVQUIRK_DISABLE_SDR104, }; static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { @@ -184,6 +197,9 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { static struct sdhci_tegra_soc_data soc_data_tegra114 = { .pdata = &sdhci_tegra114_pdata, + .nvquirks = NVQUIRK_DISABLE_SDR50 | + NVQUIRK_DISABLE_DDR50 | + NVQUIRK_DISABLE_SDR104, }; static const struct of_device_id sdhci_tegra_dt_match[] = {