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Fri, 23 May 2014 11:59:33 +0900 (KST) From: Abhilash Kesavan To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, t.figa@samsung.com Subject: [PATCH] arm: exynos: Modify pm code to check for cortex A9 rather than the SoC Date: Fri, 23 May 2014 08:31:01 +0530 Message-id: <1400814061-12813-1-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrILMWRmVeSWpSXmKPExsWyRsSkTnfazrpgg2eLOCwer1nMZDHvs6xF 74KrbBabHl9jtZhxfh+TxfoZr1kc2DzuXNvD5rF5Sb1H35ZVjB6fN8kFsERx2aSk5mSWpRbp 2yVwZVycM4m14JhYxde+s4wNjF+Fuhg5OSQETCTuTTrPDGGLSVy4t56ti5GLQ0hgKaPEvH2P 2WCKXp/7zQSRmM4ocfTmGhYIp49JYl3POxaQKjYBPYkF/76CjRIRqJC4+OYPE4jNLOAu0Xjo PSOILSwQKdHy9xxYnEVAVWLf6iOsXYwcHLwCrhJv/piDmBICChJzJtmAjJcQ+MwmsXXSEUaI cgGJb5MPsUDUyEpsOgB1tKTEwRU3WCYwCi5gZFjFKJpakFxQnJReZKhXnJhbXJqXrpecn7uJ ERicp/89693BePuA9SHGZKBxE5mlRJPzgcGdVxJvaGxmZGFqYmpsZG5pRpqwkjhv0sOkICGB 9MSS1OzU1ILUovii0pzU4kOMTBycUg2MfQvF93YefWtvVrjBK9p35fGPLuuMn9bNlzH3u/dK eM3bn4t9LVPevuC7mPd4R+7n0o8CLDp5j7h2OAhcsF/8v02k0Gb9gV8G84Uk2Lpfr5LP2/9V YOFf2YNuG2cdM12+vPbGtLnXo76uincODrCzmP6uU5drCpsXX5ShtmJ/3+94m62OGdLpSizF GYmGWsxFxYkA984P2GQCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHIsWRmVeSWpSXmKPExsVy+t9jQd2pO+uCDXYvtbF4vGYxk8W8z7IW vQuusllsenyN1WLG+X1MFutnvGZxYPO4c20Pm8fmJfUefVtWMXp83iQXwBLVwGiTkZqYklqk kJqXnJ+SmZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA7RbSaEsMacUKBSQWFys pG+HaUJoiJuuBUxjhK5vSBBcj5EBGkhYw5hxcc4k1oJjYhVf+84yNjB+Fepi5OSQEDCReH3u NxOELSZx4d56ti5GLg4hgemMEkdvrmGBcPqYJNb1vGMBqWIT0JNY8O8rM4gtIlAhcfHNH7Bu ZgF3icZD7xlBbGGBSImWv+fA4iwCqhL7Vh9h7WLk4OAVcJV488ccxJQQUJCYM8lmAiP3AkaG VYyiqQXJBcVJ6blGesWJucWleel6yfm5mxjBof9MegfjqgaLQ4wCHIxKPLwPmOqChVgTy4or cw8xSnAwK4nw+oQChXhTEiurUovy44tKc1KLDzEmA+2eyCwlmpwPjMu8knhDYxNzU2NTSxML EzNL0oSVxHkPtloHCgmkJ5akZqemFqQWwWxh4uCUamDMTOe5kyFY4jZjlsLFUEWe4+a3CyN9 ktfeyvVhldge5vJg6XfGVyJaX3L3WG95aX1zcjrTHYGYBcpyU9oXXWmS/lD34oyc1H/md7Mc 6udP1XpTWsmkr86mGdS/feX0Mo51L96WNf66cHVywurCb+z33xm+jPxeXsJv+H5hOD+/Tabn tEdPPNWVWIozEg21mIuKEwGAYd8UwQIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140522_195958_979707_88EF07EE X-CRM114-Status: GOOD ( 10.85 ) X-Spam-Score: -5.7 (-----) Cc: Abhilash Kesavan , daniel.lezcano@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We have an soc check to ensure that the scu and certain A9 specific registers are not accessed on Exynos5250 (which is A15 based). Rather than adding another soc specific check for 5420 let us test for the Cortex A9 primary part number. This resolves the below crash seen on exynos5420 during core switching after the CPUIdle consolidation series was merged. [ 155.975589] [] (scu_enable) from [] (exynos_cpu_pm_notifier+0x80/0xc4) [ 155.983833] [] (exynos_cpu_pm_notifier) from [] (notifier_call_chain+0x44/0x84) [ 155.992851] [] (notifier_call_chain) from [] (cpu_pm_notify+0x20/0x3c) [ 156.001089] [] (cpu_pm_notify) from [] (cpu_pm_exit+0x20/0x38) [ 156.008635] [] (cpu_pm_exit) from [] (bL_switcher_thread+0x298/0x40c) [ 156.016788] [] (bL_switcher_thread) from [] (kthread+0xcc/0xe8) [ 156.024426] [] (kthread) from [] (ret_from_fork+0x14/0x3c) [ 156.031621] Code: ea017fec c0530a00 c052e3f8 c0012dcc (e5903000 Signed-off-by: Abhilash Kesavan --- arch/arm/mach-exynos/pm.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index d10c351..6dd4a11 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -300,7 +300,7 @@ static int exynos_pm_suspend(void) tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); - if (!soc_is_exynos5250()) + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) exynos_cpu_save_register(); return 0; @@ -334,7 +334,7 @@ static void exynos_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - if (!soc_is_exynos5250()) + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) exynos_cpu_restore_register(); /* For release retention */ @@ -353,7 +353,7 @@ static void exynos_pm_resume(void) s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (!soc_is_exynos5250()) + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) scu_enable(S5P_VA_SCU); early_wakeup: @@ -440,15 +440,18 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self, case CPU_PM_ENTER: if (cpu == 0) { exynos_pm_central_suspend(); - exynos_cpu_save_register(); + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) + exynos_cpu_save_register(); } break; case CPU_PM_EXIT: if (cpu == 0) { - if (!soc_is_exynos5250()) + if (read_cpuid_part_number() == + ARM_CPU_PART_CORTEX_A9) { scu_enable(S5P_VA_SCU); - exynos_cpu_restore_register(); + exynos_cpu_restore_register(); + } exynos_pm_central_resume(); } break;