From patchwork Fri May 23 14:27:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 4233041 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 59F6A9F32B for ; Fri, 23 May 2014 14:30:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 490E620131 for ; Fri, 23 May 2014 14:30:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D457F20120 for ; Fri, 23 May 2014 14:30:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WnqSj-0000Ba-MO; Fri, 23 May 2014 14:28:45 +0000 Received: from mail-pb0-x22d.google.com ([2607:f8b0:400e:c01::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WnqSa-00005X-5m for linux-arm-kernel@lists.infradead.org; Fri, 23 May 2014 14:28:36 +0000 Received: by mail-pb0-f45.google.com with SMTP id um1so4225530pbc.18 for ; Fri, 23 May 2014 07:28:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=LJQBVl8V/AMud/cql0clRj3fBVmToz2h8+qUfpYFnJ8=; b=acjXJ68lEmdItZry3j25WydW/UcheDrne5LxyPt8YQw58H31ASPhmqVaVwXU905UVc iKauXiRdtiC310sOq3M383dJv6ROQLG6uiN00/3EIRY1Rr0qxYbshMaMa2aSTLc4oJI6 ek1mh2RlEfg1qHgROcvc2slZfonQO8PvtjCoF8GIjJE22+tzJWQb42zqISVFLHrE+yYO MXDksWYKFiMzSllF7Rj55JVhv0IVFUQr2XCeBdzVlDAdZXrXs/6Dyk8XxBa2B5IBHZKq P9aH/723b07BIImG48dIn5/xz4JXT/QnyR2grVsEqj38T5fozwQm9EDqPDwJHxEgqg+r kYJQ== X-Received: by 10.68.132.68 with SMTP id os4mr6305052pbb.129.1400855293082; Fri, 23 May 2014 07:28:13 -0700 (PDT) Received: from user-ubuntu.sisodomain.com ([14.140.216.146]) by mx.google.com with ESMTPSA id jd5sm4966871pbb.18.2014.05.23.07.28.07 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 23 May 2014 07:28:12 -0700 (PDT) From: Thomas Abraham To: cpufreq@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 3/7] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 Date: Fri, 23 May 2014 19:57:36 +0530 Message-Id: <1400855260-6807-4-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1400855260-6807-1-git-send-email-thomas.ab@samsung.com> References: <1400855260-6807-1-git-send-email-thomas.ab@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140523_072836_256808_00742C7C X-CRM114-Status: GOOD ( 12.12 ) X-Spam-Score: 0.0 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, l.majewski@samsung.com, kgene.kim@samsung.com, mturquette@linaro.org, heiko@sntech.de, Pawel Moll , Ian Campbell , viresh.kumar@linaro.org, t.figa@samsung.com, Rob Herring , linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com, Kumar Gala , shawn.guo@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thomas Abraham The clock blocks within the CMU_CPU clock domain are put together into a new composite clock type called the cpu clock. This clock type requires configuration data that will be atomically programmed in the multiple clock blocks encapsulated within the cpu clock type when the parent clock frequency is changed. This configuration data is held in the clock controller node. Update clock binding documentation about this configuration data format for Samsung Exynos4 and Exynos5 platforms. Cc: Tomasz Figa Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Signed-off-by: Thomas Abraham --- .../devicetree/bindings/clock/exynos4-clock.txt | 37 ++++++++++++++++++++ .../devicetree/bindings/clock/exynos5250-clock.txt | 36 +++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index f5a5b19..0934e02 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -15,6 +15,35 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + - for Exynos4210 and Exynos4212 based platforms: + cell #1: arm clock parent frequency + cell #2 ~ cell 9#: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio. + + - for Exynos4412 based platforms: + cell #1: expected arm clock parent frequency + cell #2 ~ cell #10: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio, cores_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property depends on + the SoC type. + + - for Exynos4210 and Exynos4212: the value should be 9. + - for Exynos4412: the value should be 10. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -28,6 +57,14 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1200000 3 7 3 4 1 7 5 0>, + <1000000 3 7 3 4 1 7 4 0>, + < 800000 3 7 3 3 1 7 3 0>, + < 500000 3 7 3 3 1 7 3 0>, + < 400000 3 7 3 3 1 7 3 0>, + < 200000 1 3 1 1 1 0 3 0>; }; Example 2: UART controller node that consumes the clock generated by the clock diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 536eacd..3d63d09 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -13,6 +13,24 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + cell #1: expected arm clock parent frequency + cell #2 ~ cell #9: value of clock divider in the following order + cpud_ratio, acp_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property should be 9. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -26,6 +44,24 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1700000 3 7 7 7 3 5 0 2>, + <1600000 3 7 7 7 1 4 0 2>, + <1500000 2 7 7 7 1 4 0 2>, + <1400000 2 7 7 6 1 4 0 2>, + <1300000 2 7 7 6 1 3 0 2>, + <1200000 2 7 7 5 1 3 0 2>, + <1100000 3 7 7 5 1 3 0 2>, + <1000000 1 7 7 4 1 2 0 2>, + < 900000 1 7 7 4 1 2 0 2>, + < 800000 1 7 7 4 1 2 0 2>, + < 700000 1 7 7 3 1 1 0 2>, + < 600000 1 7 7 3 1 1 0 2>, + < 500000 1 7 7 2 1 1 0 2>, + < 400000 1 7 7 2 1 1 0 2>, + < 300000 1 7 7 1 1 1 0 2>, + < 200000 1 7 7 1 1 1 0 2>; }; Example 2: UART controller node that consumes the clock generated by the clock