| Message ID | 1401403221-27523-4-git-send-email-robherring2@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, May 30, 2014 at 12:40 AM, Rob Herring <robherring2@gmail.com> wrote: > From: Rob Herring <robh@kernel.org> > > The secondary controller on ARM Versatile AB and PB is similar to > other ARM platforms, but has a pass-thru register to connect some > interrupts directly to interrupt inputs on the primary interrupt > controller. The PIC_ENABLES register needs to be configured for > proper operation when the matching node is arm,versatile-sic. Add the > the necessary IRQCHIP_DECLARE as well. > > Signed-off-by: Rob Herring <robh@kernel.org> > Cc: Thomas Gleixner <tglx@linutronix.de> > Cc: Jason Cooper <jason@lakedaemon.net> > Cc: Arnd Bergmann <arnd@arndb.de> > --- > v2: > - Rework to use the compatible string for pass-thru register setup. Nice! > + /* > + * On Versatile AB/PB, some secondary interrupts have a direct > + * pass-thru to the primary controller which need to be enabled. > + */ > + if (of_device_is_compatible(node, "arm,versatile-sic")) > + writel(0xffd00000, base + PIC_ENABLES); Maybe mention that we pass thru IRQs 20 and 22 thru 31 and why exactly these IRQs? Anyway: Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c index 8e0bb56..90bf131 100644 --- a/drivers/irqchip/irq-versatile-fpga.c +++ b/drivers/irqchip/irq-versatile-fpga.c @@ -28,6 +28,8 @@ #define FIQ_ENABLE_SET 0x28 #define FIQ_ENABLE_CLEAR 0x2C +#define PIC_ENABLES 0x20 /* set interrupt pass through bits */ + /** * struct fpga_irq_data - irq data container for the FPGA IRQ controller * @base: memory offset in virtual memory @@ -213,7 +215,15 @@ int __init fpga_irq_of_init(struct device_node *node, writel(clear_mask, base + IRQ_ENABLE_CLEAR); writel(clear_mask, base + FIQ_ENABLE_CLEAR); + /* + * On Versatile AB/PB, some secondary interrupts have a direct + * pass-thru to the primary controller which need to be enabled. + */ + if (of_device_is_compatible(node, "arm,versatile-sic")) + writel(0xffd00000, base + PIC_ENABLES); + return 0; } IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init); +IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init); #endif