From patchwork Sat Jun 14 03:00:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 4352151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E0EB2BEEAA for ; Sat, 14 Jun 2014 03:06:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0DEF320320 for ; Sat, 14 Jun 2014 03:06:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E11EF202FF for ; Sat, 14 Jun 2014 03:06:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WveG2-0007kY-I0; Sat, 14 Jun 2014 03:03:54 +0000 Received: from mail-bn1lp0144.outbound.protection.outlook.com ([207.46.163.144] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WveFy-0007ey-5D for linux-arm-kernel@lists.infradead.org; Sat, 14 Jun 2014 03:03:51 +0000 Received: from BY2FFO11FD039.protection.gbl (10.1.14.34) by BY2FFO11HUB066.protection.gbl (10.1.15.241) with Microsoft SMTP Server (TLS) id 15.0.959.15; Sat, 14 Jun 2014 03:03:26 +0000 Received: from sj-itexedge03.altera.priv.altera.com (66.35.236.227) by BY2FFO11FD039.mail.protection.outlook.com (10.1.14.224) with Microsoft SMTP Server (TLS) id 15.0.959.15 via Frontend Transport; Sat, 14 Jun 2014 03:03:26 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by sj-itexedge03.altera.priv.altera.com (66.35.236.227) with Microsoft SMTP Server id 14.3.174.1; Fri, 13 Jun 2014 20:02:11 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.79]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id s5E33ObJ028141; Fri, 13 Jun 2014 20:03:25 -0700 (PDT) From: To: Subject: [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk Date: Fri, 13 Jun 2014 22:00:35 -0500 Message-ID: <1402714835-19861-1-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:66.35.236.227; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(68736004)(102836001)(31966008)(19580405001)(81342001)(62966002)(21056001)(83322001)(74662001)(6806004)(84676001)(77156001)(44976005)(87286001)(81542001)(80022001)(19580395003)(74502001)(36756003)(53416003)(99396002)(50466002)(104166001)(33646001)(89996001)(4396001)(50226001)(46102001)(92566001)(92726001)(93916002)(86362001)(88136002)(79102001)(87936001)(83072002)(97736001)(48376002)(86152002)(76482001)(85852003)(50986999)(47776003)(77982001)(20776003)(64706001); DIR:OUT; SFP:; SCL:1; SRVR:BY2FFO11HUB066; H:sj-itexedge03.altera.priv.altera.com; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-OriginatorOrg: altera.onmicrosoft.com X-Microsoft-Antispam: BL:0; ACTION:Default; RISK:Low; SCL:0; SPMLVL:NotSpam; PCL:0; RULEID: X-Forefront-PRVS: 02426D11FE Received-SPF: SoftFail (: domain of transitioning altera.com discourages use of 66.35.236.227 as permitted sender) Authentication-Results: spf=softfail (sender IP is 66.35.236.227) smtp.mailfrom=dinguyen@altera.com; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140613_200350_406692_68EE787C X-CRM114-Status: GOOD ( 10.13 ) X-Spam-Score: -0.0 (/) Cc: dinh.linux@gmail.com, Dinh Nguyen , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen --- v2: Update socfpga_periph_init to support multiple parents --- arch/arm/boot/dts/socfpga.dtsi | 2 +- drivers/clk/socfpga/clk-periph.c | 21 +++++++++++++++++---- drivers/clk/socfpga/clk.h | 1 + 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 291eff1..26d755b 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -139,7 +139,7 @@ dbg_base_clk: dbg_base_clk { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; + clocks = <&main_pll>, <&osc1>; div-reg = <0xe8 0 9>; reg = <0x50>; }; diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c index 46531c3..9b64847 100644 --- a/drivers/clk/socfpga/clk-periph.c +++ b/drivers/clk/socfpga/clk-periph.c @@ -45,8 +45,17 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk, return parent_rate / div; } +static u8 clk_periclk_get_parent(struct clk_hw *hwclk) +{ + u32 clk_src; + + clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL); + return clk_src & 0x1; +} + static const struct clk_ops periclk_ops = { .recalc_rate = clk_periclk_recalc_rate, + .get_parent = clk_periclk_get_parent, }; static __init void __socfpga_periph_init(struct device_node *node, @@ -56,11 +65,12 @@ static __init void __socfpga_periph_init(struct device_node *node, struct clk *clk; struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; - const char *parent_name; + const char *parent_name[SOCFPGA_MAX_PARENTS]; struct clk_init_data init; int rc; u32 fixed_div; u32 div_reg[3]; + int i = 0; of_property_read_u32(node, "reg", ®); @@ -90,9 +100,12 @@ static __init void __socfpga_periph_init(struct device_node *node, init.name = clk_name; init.ops = ops; init.flags = 0; - parent_name = of_clk_get_parent_name(node, 0); - init.parent_names = &parent_name; - init.num_parents = 1; + while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] = + of_clk_get_parent_name(node, i)) != NULL) + i++; + + init.parent_names = parent_name; + init.num_parents = i; periph_clk->hw.hw.init = &init; diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index d291f60..d036de2 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -23,6 +23,7 @@ /* Clock Manager offsets */ #define CLKMGR_CTRL 0x0 #define CLKMGR_BYPASS 0x4 +#define CLKMGR_DBCTRL 0x10 #define CLKMGR_L4SRC 0x70 #define CLKMGR_PERPLL_SRC 0xAC