From patchwork Tue Jun 17 18:36:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 4369701 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 450AFBEEAA for ; Tue, 17 Jun 2014 18:39:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5A5E2201DD for ; Tue, 17 Jun 2014 18:39:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65383201D3 for ; Tue, 17 Jun 2014 18:39:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WwyG6-0007bH-Dj; Tue, 17 Jun 2014 18:37:26 +0000 Received: from smtp.codeaurora.org ([198.145.11.231]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WwyG0-0007RM-Or for linux-arm-kernel@lists.infradead.org; Tue, 17 Jun 2014 18:37:22 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 0DB5F1407E5; Tue, 17 Jun 2014 18:37:00 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id F40111407F3; Tue, 17 Jun 2014 18:36:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from galak-ubuntu.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: galak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0C5411407E5; Tue, 17 Jun 2014 18:36:58 +0000 (UTC) From: Kumar Gala To: Tejun Heo Subject: [PATCH v3 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver Date: Tue, 17 Jun 2014 13:36:57 -0500 Message-Id: <1403030217-21554-1-git-send-email-galak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140617_113720_858252_069F4E69 X-CRM114-Status: GOOD ( 19.60 ) X-Spam-Score: -1.0 (-) Cc: b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org, Kumar Gala , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the Qualcomm AHCI SATA controller that exists on several SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support requires the associated IPQ806x SATA PHY Driver to be enabled as well. Signed-off-by: Kumar Gala tested-by: Kiran Padwal --- v3: * Added comment about suspend/resume not supported * Fixup ahci_platform_init_host for upstream change to interface * cleanup error handling of rxoob clk, moved to devm_clk_get/put v2: * Fixed MODULE_LICENSE to be GPL v2 drivers/ata/Kconfig | 10 ++++++ drivers/ata/Makefile | 1 + drivers/ata/ahci_qcom.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 drivers/ata/ahci_qcom.c diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 7671dba..aa88648 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -132,6 +132,16 @@ config AHCI_MVEBU If unsure, say N. +config AHCI_QCOM + tristate "Qualcomm AHCI SATA support" + depends on ARCH_QCOM + help + This option enables support for AHCI SATA controller + integrated into Qualcomm ARM SoC chipsets. For more + information please refer to http://www.qualcomm.com/chipsets. + + If unsure, say N. + config AHCI_SUNXI tristate "Allwinner sunxi AHCI SATA support" depends on ARCH_SUNXI diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 5a02aee..15401e9 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o +obj-$(CONFIG_AHCI_QCOM) += ahci_qcom.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o diff --git a/drivers/ata/ahci_qcom.c b/drivers/ata/ahci_qcom.c new file mode 100644 index 0000000..412e878 --- /dev/null +++ b/drivers/ata/ahci_qcom.c @@ -0,0 +1,90 @@ +/* + * Qualcomm ARM SoC AHCI SATA platform driver + * + * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov + * + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ahci.h" + +static const struct ata_port_info qcom_ahci_port_info = { + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_platform_ops, +}; + +static int qcom_ahci_probe(struct platform_device *pdev) +{ + struct ahci_host_priv *hpriv; + struct clk *rxoob_clk; + int rc; + + hpriv = ahci_platform_get_resources(pdev); + if (IS_ERR(hpriv)) + return PTR_ERR(hpriv); + + /* Try and set the rxoob clk to 100Mhz */ + rxoob_clk = devm_clk_get(&pdev->dev, "rxoob"); + if (IS_ERR(rxoob_clk)) + return PTR_ERR(rxoob_clk); + + rc = clk_set_rate(rxoob_clk, 100000000); + if (rc) + return rc; + + devm_clk_put(&pdev->dev, rxoob_clk); + + rc = ahci_platform_enable_resources(hpriv); + if (rc) + return rc; + + rc = ahci_platform_init_host(pdev, hpriv, &qcom_ahci_port_info, + 0, 0, 0); + if (rc) + goto disable_resources; + + return 0; +disable_resources: + ahci_platform_disable_resources(hpriv); + return rc; +} + +static const struct of_device_id qcom_ahci_of_match[] = { + { .compatible = "qcom,msm-ahci", }, + {}, +}; +MODULE_DEVICE_TABLE(of, qcom_ahci_of_match); + +static struct platform_driver qcom_ahci_driver = { + .probe = qcom_ahci_probe, + .remove = ata_platform_remove_one, + .driver = { + .name = "qcom_ahci_qcom", + .owner = THIS_MODULE, + .of_match_table = qcom_ahci_of_match, + }, + /* suspend/resume not currently supported */ +}; +module_platform_driver(qcom_ahci_driver); + +MODULE_DESCRIPTION("Qualcomm AHCI SATA platform driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("ahci:qcom");