From patchwork Mon Jun 23 08:42:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 4400281 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 038769F1D6 for ; Mon, 23 Jun 2014 08:47:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1D8D920279 for ; Mon, 23 Jun 2014 08:47:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3922C2013A for ; Mon, 23 Jun 2014 08:47:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WyzsG-0005C6-1f; Mon, 23 Jun 2014 08:45:12 +0000 Received: from mail-bl2ln0123.outbound.protection.outlook.com ([2a01:111:f400:7c09::123] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WyzsA-000427-UG for linux-arm-kernel@lists.infradead.org; Mon, 23 Jun 2014 08:45:09 +0000 Received: from BY2PR03CA041.namprd03.prod.outlook.com (10.141.249.14) by BY2PR03MB348.namprd03.prod.outlook.com (10.141.139.22) with Microsoft SMTP Server (TLS) id 15.0.954.9; Mon, 23 Jun 2014 08:44:19 +0000 Received: from BL2FFO11FD013.protection.gbl (2a01:111:f400:7c09::179) by BY2PR03CA041.outlook.office365.com (2a01:111:e400:2c5d::14) with Microsoft SMTP Server (TLS) id 15.0.969.15 via Frontend Transport; Mon, 23 Jun 2014 08:44:19 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11FD013.mail.protection.outlook.com (10.173.160.221) with Microsoft SMTP Server (TLS) id 15.0.969.12 via Frontend Transport; Mon, 23 Jun 2014 08:44:19 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s5N8iGoR009313; Mon, 23 Jun 2014 01:44:17 -0700 From: Anson Huang To: , Subject: [PATCH 1/2] ARM: imx: mem bit must be cleared before entering DSM mode Date: Mon, 23 Jun 2014 16:42:43 +0800 Message-ID: <1403512964-19095-1-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(43544003)(189002)(199002)(77982001)(81342001)(50226001)(64706001)(31966008)(44976005)(21056001)(575784001)(47776003)(50986999)(80022001)(76482001)(68736004)(46102001)(50466002)(99396002)(93916002)(62966002)(26826002)(81542001)(36756003)(106466001)(19580395003)(6806004)(104016002)(95666004)(48376002)(84676001)(105606002)(74662001)(74502001)(83072002)(85852003)(4396001)(104166001)(85306003)(92726001)(79102001)(19580405001)(89996001)(97736001)(88136002)(33646001)(87936001)(87286001)(102836001)(77156001)(92566001)(20776003)(83322001)(42262001); DIR:OUT; SFP:; SCL:1; SRVR:BY2PR03MB348; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BL:0; ACTION:Default; RISK:Low; SCL:0; SPMLVL:NotSpam; PCL:0; RULEID: X-Forefront-PRVS: 025100C802 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Anson.Huang@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140623_014507_244414_3D5A1DD8 X-CRM114-Status: UNSURE ( 9.49 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to hardware design, mem bit must be clear before entering DSM mode, as ARM core will be power gated in DSM mode. Signed-off-by: Anson Huang --- arch/arm/mach-imx/common.h | 2 +- arch/arm/mach-imx/cpuidle-imx6q.c | 2 +- arch/arm/mach-imx/pm-imx6.c | 8 ++++++-- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 50ee9c2..13a6e1f 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -116,7 +116,7 @@ void imx_anatop_init(void); void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -void imx6q_set_int_mem_clk_lpm(void); +void imx6q_set_int_mem_clk_lpm(bool enable); void imx6sl_set_wait_clk(bool enter); void imx_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index fc0bb1e..10844d3 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -71,7 +71,7 @@ int __init imx6q_cpuidle_init(void) imx_scu_standby_enable(); /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ - imx6q_set_int_mem_clk_lpm(); + imx6q_set_int_mem_clk_lpm(true); return cpuidle_register(&imx6q_cpuidle_driver, NULL); } diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 331055b..b3c770d 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -199,11 +199,13 @@ struct imx6_cpu_pm_info { u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ } __aligned(8); -void imx6q_set_int_mem_clk_lpm(void) +void imx6q_set_int_mem_clk_lpm(bool enable) { u32 val = readl_relaxed(ccm_base + CGPR); - val |= BM_CGPR_INT_MEM_CLK_LPM; + val &= ~BM_CGPR_INT_MEM_CLK_LPM; + if (enable) + val |= BM_CGPR_INT_MEM_CLK_LPM; writel_relaxed(val, ccm_base + CGPR); } @@ -334,6 +336,7 @@ static int imx6q_pm_enter(suspend_state_t state) switch (state) { case PM_SUSPEND_MEM: imx6q_set_lpm(STOP_POWER_OFF); + imx6q_set_int_mem_clk_lpm(false); imx6q_enable_wb(true); /* * For suspend into ocram, asm code already take care of @@ -352,6 +355,7 @@ static int imx6q_pm_enter(suspend_state_t state) imx_gpc_post_resume(); imx6q_enable_rbc(false); imx6q_enable_wb(false); + imx6q_set_int_mem_clk_lpm(true); imx6q_set_lpm(WAIT_CLOCKED); break; default: