diff mbox

[3/6] clk: samsung: exynos4: Remove SRC_MASK_ISP gates

Message ID 1403618235-19353-4-git-send-email-t.figa@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Tomasz Figa June 24, 2014, 1:57 p.m. UTC
ISP special clocks have dedicated gating registers and so MUX SRC_MASK
register should not be used. This patch fixes the problem of
Exynos4x12-based boards freezing on system suspend, because those
mux outputs need not to be masked while suspending.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
---
 drivers/clk/samsung/clk-exynos4.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

Comments

Daniel Drake June 25, 2014, 9:58 a.m. UTC | #1
Hi Tomasz,

On Tue, Jun 24, 2014 at 2:57 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> ISP special clocks have dedicated gating registers and so MUX SRC_MASK
> register should not be used. This patch fixes the problem of
> Exynos4x12-based boards freezing on system suspend, because those
> mux outputs need not to be masked while suspending.

Not sure if you will be interested in this, as your plate must be
pretty full already, and I am probably the first person to try
suspend/resume on ODROID, but:

ODROID-U2 fails to suspend/resume. I am testing with rtcwake, trying
to raise a wakeup alarm on the internal Exynos4412 RTC. For this,
CONFIG_COMMON_CLK_MAX77686 must be disabled (otherwise it disables the
upstream 32KHz clock source for the RTC), I also have
CONFIG_RTC_DRV_MAX77686 disabled so that there is only one RTC to
worry about.

Then:
 rtcwake --utc -m mem -s 10 -v

Before this patch, it would totally hang after calling cpu_suspend()
(checked with S3C_PMDBG) - not sure if it hangs before sleeping, or if
it sleeps but simply fails to wake up.

With this patch, now it seems like the RTC alarm does wake up the
system after the desired time, however it immediately goes back into
uboot rather than resuming into Linux. So this patch does make some
progress at least.

The power light is on at all times during these tests (not sure if
that means anything, but I was wondering if it should go out when the
system suspends).

Thanks
Daniel
Tomasz Figa June 25, 2014, 10:10 a.m. UTC | #2
Hi Daniel,

On 25.06.2014 11:58, Daniel Drake wrote:
> Hi Tomasz,
> 
> On Tue, Jun 24, 2014 at 2:57 PM, Tomasz Figa <t.figa@samsung.com> wrote:
>> ISP special clocks have dedicated gating registers and so MUX SRC_MASK
>> register should not be used. This patch fixes the problem of
>> Exynos4x12-based boards freezing on system suspend, because those
>> mux outputs need not to be masked while suspending.
> 
> Not sure if you will be interested in this, as your plate must be
> pretty full already, and I am probably the first person to try
> suspend/resume on ODROID, but:
> 
> ODROID-U2 fails to suspend/resume. I am testing with rtcwake, trying
> to raise a wakeup alarm on the internal Exynos4412 RTC. For this,
> CONFIG_COMMON_CLK_MAX77686 must be disabled (otherwise it disables the
> upstream 32KHz clock source for the RTC), I also have
> CONFIG_RTC_DRV_MAX77686 disabled so that there is only one RTC to
> worry about.
> 
> Then:
>  rtcwake --utc -m mem -s 10 -v
> 
> Before this patch, it would totally hang after calling cpu_suspend()
> (checked with S3C_PMDBG) - not sure if it hangs before sleeping, or if
> it sleeps but simply fails to wake up.
> 
> With this patch, now it seems like the RTC alarm does wake up the
> system after the desired time, however it immediately goes back into
> uboot rather than resuming into Linux. So this patch does make some
> progress at least.
> 
> The power light is on at all times during these tests (not sure if
> that means anything, but I was wondering if it should go out when the
> system suspends).

As far as I'm aware of, all Exynos4412-based ODROIDs run secure
firmware, which needs special handling of suspend/resume. I already have
a series to address this, but there is one more issue that I'd like to
fix, until I send it. The patches should hit the ML this week, though.

Best regards,
Tomasz
Tomasz Figa June 30, 2014, 1:50 p.m. UTC | #3
On 24.06.2014 15:57, Tomasz Figa wrote:
> ISP special clocks have dedicated gating registers and so MUX SRC_MASK
> register should not be used. This patch fixes the problem of
> Exynos4x12-based boards freezing on system suspend, because those
> mux outputs need not to be masked while suspending.
> 
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> ---
>  drivers/clk/samsung/clk-exynos4.c | 16 ++++------------
>  1 file changed, 4 insertions(+), 12 deletions(-)

Applied as a fix for 3.16.

Best regards,
Tomasz
diff mbox

Patch

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 4f150c9..7f4a473 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -925,21 +925,13 @@  static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
 	GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
 			0, 0),
 	GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
-	GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp",
-			E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
-	GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre",
-			E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
-	GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre",
-			E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
-	GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
-			E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
-	GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp",
+	GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
 			E4X12_GATE_IP_ISP, 0, 0, 0),
-	GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp",
+	GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
 			E4X12_GATE_IP_ISP, 1, 0, 0),
-	GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp",
+	GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
 			E4X12_GATE_IP_ISP, 2, 0, 0),
-	GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp",
+	GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
 			E4X12_GATE_IP_ISP, 3, 0, 0),
 	GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
 	GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,