From patchwork Wed Jun 25 13:37:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 4420871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3F73C9F1D6 for ; Wed, 25 Jun 2014 13:41:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5D1AA201B4 for ; Wed, 25 Jun 2014 13:41:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 33DBD2009C for ; Wed, 25 Jun 2014 13:41:11 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WznPW-0007qC-KL; Wed, 25 Jun 2014 13:38:50 +0000 Received: from mailout2.w1.samsung.com ([210.118.77.12]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WznPN-0007Zo-8L for linux-arm-kernel@lists.infradead.org; Wed, 25 Jun 2014 13:38:41 +0000 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N7Q00LIY8JDSH10@mailout2.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 25 Jun 2014 14:38:01 +0100 (BST) X-AuditID: cbfec7f4-b7fac6d000006cfe-55-53aad0c889a8 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id DE.8B.27902.8C0DAA35; Wed, 25 Jun 2014 14:38:16 +0100 (BST) Received: from AMDC1227.digital.local ([106.116.147.199]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0N7Q00AH88JOVV90@eusync2.samsung.com>; Wed, 25 Jun 2014 14:38:16 +0100 (BST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 1/6] ARM: mm: cache-l2x0: Add base address argument to write_sec callback Date: Wed, 25 Jun 2014 15:37:26 +0200 Message-id: <1403703451-12233-2-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.9.3 In-reply-to: <1403703451-12233-1-git-send-email-t.figa@samsung.com> References: <1403703451-12233-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHLMWRmVeSWpSXmKPExsVy+t/xK7onLqwKNpj6R9ji0fzHzBa9C66y WWzvnMFuMeXPciaLTY+vsVpc3jWHzWL2kn4Wixnn9zFZ3L7Ma7H2yF12i9d9a5gt1s94zWKx atcfRov9V7wc+DxamnvYPL59ncTicbmvl8lj0fcsj52z7rJ73Lm2h81j85J6j74tqxg9jt/Y zuTxeZNcAFcUl01Kak5mWWqRvl0CV8bxjedZC2bJVXQ2fGJuYJwn2cXIwSEhYCLRO92ui5ET yBSTuHBvPVsXIxeHkMBSRolv1+8xQjh9TBKL5t5iBaliE1CT+NzwiA3EFhFQlfjctoAdpIhZ oIFF4krrdbCEsECcxI2lT1lAbBagovnH9oM18wo4SfRt3sAMsU5OonfbGzCbU8BZ4sK8P2A1 QkA1854cYZzAyLuAkWEVo2hqaXJBcVJ6rqFecWJucWleul5yfu4mRkgYf9nBuPiY1SFGAQ5G JR7eAJ5VwUKsiWXFlbmHGCU4mJVEeN33A4V4UxIrq1KL8uOLSnNSiw8xMnFwSjUw8vwWMA2a cGr91hLVmLeFPwV9vz0tkdBY8N8wOvrd/6h7NzvCKlbvZX789LbR+4erI+6EHUg/fOve/K7D tYvK+zepbAssMMs8EqR5INPcp/7KW8dpU/33ldZu25wa0db/4JHrqd81qduFX7oK7ih87e+f 1WH5X1f5U0vk9QxLr1nWR4/e/PhVVImlOCPRUIu5qDgRAI7b96JBAgAA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140625_063841_454212_CE0C4BAD X-CRM114-Status: GOOD ( 13.73 ) X-Spam-Score: -5.0 (-----) Cc: Kukjin Kim , Laura Abbott , Tony Lindgren , Linus Walleij , linux-kernel@vger.kernel.org, Tomasz Figa , Tomasz Figa , Santosh Shilimkar , Russell King - ARM Linux , linux-omap@vger.kernel.org, Daniel Drake , linux-arm-kernel@lists.infradead.org, Marek Szyprowski X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For certain platforms (e.g. Exynos) it is necessary to read back some values from registers before they can be written (i.e. SMC calls that set multiple registers per call), so base address of L2C controller is needed for .write_sec operation. This patch adds base argument to .write_sec callback so that its implementation can also access registers directly. Signed-off-by: Tomasz Figa Acked-by: Linus Walleij --- arch/arm/include/asm/mach/arch.h | 3 ++- arch/arm/include/asm/outercache.h | 2 +- arch/arm/mach-highbank/highbank.c | 3 ++- arch/arm/mach-omap2/omap4-common.c | 3 ++- arch/arm/mach-ux500/cache-l2x0.c | 3 ++- arch/arm/mm/cache-l2x0.c | 2 +- 6 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index 060a75e..fefff4d 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -46,7 +46,8 @@ struct machine_desc { enum reboot_mode reboot_mode; /* default restart mode */ unsigned l2c_aux_val; /* L2 cache aux value */ unsigned l2c_aux_mask; /* L2 cache aux mask */ - void (*l2c_write_sec)(unsigned long, unsigned); + void (*l2c_write_sec)(unsigned long, + void __iomem *, unsigned); struct smp_operations *smp; /* SMP operations */ bool (*smp_init)(void); void (*fixup)(struct tag *, char **); diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index 891a56b..25b70b5 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -35,7 +35,7 @@ struct outer_cache_fns { void (*resume)(void); /* This is an ARM L2C thing */ - void (*write_sec)(unsigned long, unsigned); + void (*write_sec)(unsigned long, void __iomem *, unsigned); }; extern struct outer_cache_fns outer_cache; diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index 8c35ae4..20cf160 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -51,7 +51,8 @@ static void __init highbank_scu_map_io(void) } -static void highbank_l2c310_write_sec(unsigned long val, unsigned reg) +static void highbank_l2c310_write_sec(unsigned long val, void __iomem *base, + unsigned reg) { if (reg == L2X0_CTRL) highbank_smc1(0x102, val); diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 326cd98..ce04afa 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -167,7 +167,8 @@ void __iomem *omap4_get_l2cache_base(void) return l2cache_base; } -static void omap4_l2c310_write_sec(unsigned long val, unsigned reg) +static void omap4_l2c310_write_sec(unsigned long val, void __iomem *base, + unsigned reg) { unsigned smc_op; diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 842ebed..bd87108 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -35,7 +35,8 @@ static int __init ux500_l2x0_unlock(void) return 0; } -static void ux500_l2c310_write_sec(unsigned long val, unsigned reg) +static void ux500_l2c310_write_sec(unsigned long val, void __iomem *base, + unsigned reg) { /* * We can't write to secure registers as we are in non-secure diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index efc5cab..478566b 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -72,7 +72,7 @@ static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) if (val == readl_relaxed(base + reg)) return; if (outer_cache.write_sec) - outer_cache.write_sec(val, reg); + outer_cache.write_sec(val, base, reg); else writel_relaxed(val, base + reg); }