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Thu, 26 Jun 2014 20:14:41 +0900 (KST) From: Vikas Sajjan To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v5 3/3] clk: samsung: exynos5420: Setup clocks before system suspend Date: Thu, 26 Jun 2014 16:42:15 +0530 Message-id: <1403781135-6538-4-git-send-email-vikas.sajjan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1403781135-6538-1-git-send-email-vikas.sajjan@samsung.com> References: <1403781135-6538-1-git-send-email-vikas.sajjan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrDLMWRmVeSWpSXmKPExsWyRsSkWnchw5pgg5P9QhaP1yxmsji77CCb xfddX9gtehdcZbPY9Pgaq8WM8/uYLJ4c/shqsWrXH0aLm8+2MzlwesxuuMjisXPWXXaPzUvq Pfq2rGL0+LxJLoA1issmJTUnsyy1SN8ugSvj6IxutoIpUhWz511maWDcKdrFyMEhIWAi0d2v 0sXICWSKSVy4t56ti5GLQ0hgKaPEnEPnmCESJhLTGpewQCQWMUos2bGZGcKZwCTRsmMhE0gV m4CuxIpTz9lApooIeEssv6YIEmYWOM0o0dpjCmILC4RJXJm4jRGkhEVAVWLjJFGQMK+Au8T/ i9uZIe5RkJgzyQYkzCngIdE/czcjiC0EVPKy/yLYCRICq9gljnzbzAaSYBEQkPg2+RALRK+s xKYDUCdLShxccYNlAqPwAkaGVYyiqQXJBcVJ6UVGesWJucWleel6yfm5mxiBIX/637O+HYw3 D1gfYkwGGjeRWUo0OR8YM3kl8YbGZkYWpiamxkbmlmakCSuJ8y56mBQkJJCeWJKanZpakFoU X1Sak1p8iJGJg1OqgdHWy4adxbvtvnlponXyU7mi9clJbZuXzTdI0MhY9kNf+/ROv9CAWd9l FWU2zvsX5VPc7vIue+4ZueKMfVmL3pn99VPZ2HHCdFbvFFbNNb9TbXU8u16XLbyQ3jlPraIu +qvICzuJpypPGlnqLi3r3jjvVAD/LPPFmlw3NtuKB6Xf53uTJVfBoMRSnJFoqMVcVJwIAPCH uJSPAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDIsWRmVeSWpSXmKPExsVy+t9jAd2FDGuCDRZO4LJ4vGYxk8XZZQfZ LL7v+sJu0bvgKpvFpsfXWC1mnN/HZPHk8EdWi1W7/jBa3Hy2ncmB02N2w0UWj52z7rJ7bF5S 79G3ZRWjx+dNcgGsUQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2 Si4+AbpumTlABykplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCWsYM47O6GYr mCJVMXveZZYGxp2iXYycHBICJhLTGpewQNhiEhfurWfrYuTiEBJYxCixZMdmZghnApNEy46F TCBVbAK6EitOPQeq4uAQEfCWWH5NESTMLHCaUaK1xxTEFhYIk7gycRsjSAmLgKrExklgu3gF 3CX+X9zODBKWEFCQmDPJBiTMKeAh0T9zNyOILQRU8rL/IssERt4FjAyrGEVTC5ILipPScw31 ihNzi0vz0vWS83M3MYJj6pnUDsaVDRaHGAU4GJV4eD88XhUsxJpYVlyZe4hRgoNZSYRX5Pfq YCHelMTKqtSi/Pii0pzU4kOMpkA3TWSWEk3OB8Z7Xkm8obGJuamxqaWJhYmZpZI474FW60Ah gfTEktTs1NSC1CKYPiYOTqkGxqpkRi+L08W8cyfv4o3/2OWVWJ59jXfG4hmV0mZsN/r6c4t2 FCx/VMQb9+HEtWfvp575daj9ofpuCalFrofeJwn/kIjaZyVyy+jvpveCPEqehTbXxbbeu9fx M0YtRUz5y2+viLvvI4VXdZXMU3R+ydpgs1bG2N2SyeGRj9cmMc+syX/nvTd5qMRSnJFoqMVc VJwIAA/AqV6/AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140626_041501_012173_3DA24BA7 X-CRM114-Status: GOOD ( 10.14 ) X-Spam-Score: -5.0 (-----) Cc: sajjan.linux@gmail.com, kgene.kim@samsung.com, tomasz.figa@gmail.com, dianders@chromium.org, Abhilash Kesavan , Vikas Sajjan , joshi@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Prior to suspending the system, we need to ensure that certain clock source and gate registers are unmasked. while at it, add these clks to save/restore list also. Signed-off-by: Vikas Sajjan Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-exynos5420.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 9d7d7ee..7e87d7c 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -28,6 +28,7 @@ #define GATE_BUS_CPU 0x700 #define GATE_SCLK_CPU 0x800 #define CLKOUT_CMU_CPU 0xa00 +#define SRC_MASK_CPERI 0x4300 #define GATE_IP_G2D 0x8800 #define CPLL_LOCK 0x10020 #define DPLL_LOCK 0x10030 @@ -70,6 +71,8 @@ #define SRC_TOP11 0x10284 #define SRC_TOP12 0x10288 #define SRC_TOP13 0x1028c /* 5800 specific */ +#define SRC_MASK_TOP0 0x10300 +#define SRC_MASK_TOP1 0x10304 #define SRC_MASK_TOP2 0x10308 #define SRC_MASK_TOP7 0x1031c #define SRC_MASK_DISP10 0x1032c @@ -77,6 +80,7 @@ #define SRC_MASK_FSYS 0x10340 #define SRC_MASK_PERIC0 0x10350 #define SRC_MASK_PERIC1 0x10354 +#define SRC_MASK_ISP 0x10370 #define DIV_TOP0 0x10500 #define DIV_TOP1 0x10504 #define DIV_TOP2 0x10508 @@ -98,6 +102,7 @@ #define DIV2_RATIO0 0x10590 #define DIV4_RATIO 0x105a0 #define GATE_BUS_TOP 0x10700 +#define GATE_BUS_DISP1 0x10728 #define GATE_BUS_GEN 0x1073c #define GATE_BUS_FSYS0 0x10740 #define GATE_BUS_FSYS2 0x10748 @@ -190,6 +195,10 @@ static unsigned long exynos5x_clk_regs[] __initdata = { SRC_MASK_FSYS, SRC_MASK_PERIC0, SRC_MASK_PERIC1, + SRC_MASK_TOP0, + SRC_MASK_TOP1, + SRC_MASK_MAU, + SRC_MASK_ISP, SRC_ISP, DIV_TOP0, DIV_TOP1, @@ -208,6 +217,7 @@ static unsigned long exynos5x_clk_regs[] __initdata = { SCLK_DIV_ISP1, DIV2_RATIO0, DIV4_RATIO, + GATE_BUS_DISP1, GATE_BUS_TOP, GATE_BUS_GEN, GATE_BUS_FSYS0, @@ -249,6 +259,22 @@ static unsigned long exynos5800_clk_regs[] __initdata = { GATE_IP_CAM, }; +static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { + { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, + { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, + { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, + { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, + { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, + { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, + { .offset = SRC_MASK_MAU, .value = 0x10000000, }, + { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, + { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, + { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, + { .offset = SRC_MASK_ISP, .value = 0x11111000, }, + { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, + { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, +}; + static int exynos5420_clk_suspend(void) { samsung_clk_save(reg_base, exynos5x_save, @@ -258,6 +284,9 @@ static int exynos5420_clk_suspend(void) samsung_clk_save(reg_base, exynos5800_save, ARRAY_SIZE(exynos5800_clk_regs)); + samsung_clk_restore(reg_base, exynos5420_set_clksrc, + ARRAY_SIZE(exynos5420_set_clksrc)); + return 0; }