From patchwork Sun Jun 29 18:32:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Jarzmik X-Patchwork-Id: 4444981 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A41B4BEEAA for ; Sun, 29 Jun 2014 18:35:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 974C220379 for ; Sun, 29 Jun 2014 18:35:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7F45720353 for ; Sun, 29 Jun 2014 18:35:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X1JvF-0002mX-Gt; Sun, 29 Jun 2014 18:33:53 +0000 Received: from smtp01.smtpout.orange.fr ([80.12.242.123] helo=smtp.smtpout.orange.fr) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X1Jv4-0002iN-NC for linux-arm-kernel@lists.infradead.org; Sun, 29 Jun 2014 18:33:44 +0000 Received: from localhost.localdomain ([90.38.42.162]) by mwinf5d53 with ME id LJZB1o00B3Vvi2203JZP27; Sun, 29 Jun 2014 20:33:25 +0200 X-ME-Helo: localhost.localdomain X-ME-Date: Sun, 29 Jun 2014 20:33:25 +0200 X-ME-IP: 90.38.42.162 From: Robert Jarzmik To: devicetree@vger.kernel.org, Mike Turquette , Haojian Zhuang , Eric Miao Subject: [PATCH 2/4] dts: add devicetree bindings for pxa27x clocks Date: Sun, 29 Jun 2014 20:32:22 +0200 Message-Id: <1404066744-13416-3-git-send-email-robert.jarzmik@free.fr> X-Mailer: git-send-email 2.0.0.rc2 In-Reply-To: <1404066744-13416-1-git-send-email-robert.jarzmik@free.fr> References: <1404066744-13416-1-git-send-email-robert.jarzmik@free.fr> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140629_113343_222750_16FD4A5E X-CRM114-Status: GOOD ( 12.54 ) X-Spam-Score: -2.0 (--) Cc: Mark Rutland , Robert Jarzmik , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the clock tree description for the PXA27x based boards. Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa27x.dtsi | 134 ++++++++++++++++++++++++++++++- include/dt-bindings/clock/pxa2xx-clock.h | 45 +++++++++++ 2 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/pxa2xx-clock.h diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index a705469..badaa71 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -1,5 +1,6 @@ /* The pxa3xx skeleton simply augments the 2xx version */ -/include/ "pxa2xx.dtsi" +#include "pxa2xx.dtsi" +#include "dt-bindings/clock/pxa2xx-clock.h" / { model = "Marvell PXA27x familiy SoC"; @@ -35,4 +36,135 @@ #pwm-cells = <1>; }; }; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc13mhz:osc13mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <13000000>; + }; + + osc32_768khz:osc32_768khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + pll_312mhz:pll_312mhz { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&osc13mhz>; + clock-div = <1>; + clock-mult = <24>; + }; + + clk_48mhz:clk_48mhz { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll_312mhz>; + clock-div = <13>; + clock-mult = <2>; + }; + + clk_32_842mhz:clk_32_842mhz { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll_312mhz>; + clock-div = <19>; + clock-mult = <2>; + }; + + clk_19_5mhz:clk_19_5mhz { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll_312mhz>; + clock-div = <32>; + clock-mult = <2>; + }; + + clk_14_857mhz:clk_14_857mhz { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll_312mhz>; + clock-div = <42>; + clock-mult = <2>; + }; + + clk_14_682mhz:clk_14_682mhz { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&pll_312mhz>; + clock-div = <51>; + clock-mult = <2>; + }; + + clk_13mhz:clk_13mhz { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&osc13mhz>; + clock-div = <1>; + clock-mult = <1>; + }; + + clk_dummy:clk_dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + clk_ostimer:clk_ostimer { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&osc13mhz>; + clock-div = <4>; + clock-mult = <1>; + }; + + pxa27x_sysclks:pxa27x_sysclks { + compatible = "marvell,pxa270-core-clocks"; + #clock-cells = <1>; + clocks = <&osc13mhz>; + clock-output-names = "run mode", "half-turbo mode", + "turbo mode", "cpu core", "system bus", "memory", "lcd"; + }; + + pxa2xx_clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa-clocks"; + reg = <0x41300004 0x4>; + clocks = + <&clk_13mhz>, <&clk_13mhz>, <&clk_dummy>, <&clk_13mhz>, + <&clk_13mhz>, <&clk_14_857mhz>, <&clk_14_857mhz>, <&clk_14_857mhz>, + <&clk_14_682mhz>, <&clk_ostimer>, <&clk_48mhz>, <&clk_48mhz>, + <&clk_19_5mhz>, <&clk_48mhz>, <&clk_32_842mhz>, <&clk_13mhz>, + <&pxa27x_sysclks 6>, <&clk_48mhz>, <&clk_48mhz>, <&osc32_768khz>, + <&clk_dummy>, <&clk_19_5mhz>, <&pxa27x_sysclks 4>, <&clk_13mhz>, + <&pxa27x_sysclks 6>, <&clk_dummy>; + #clock-cells = <1>; + clock-output-names = + "pwm 0,2", "pwm 1,3", "ac97", "ssp2", + "ssp3,hwuart", "stuart", "ffuart", "btuart", + "i2s", "nssp,ostimer", "usb host,assp", "usb udc", + "mmc", "ficp", "i2c", "pwri2c", + "lcd", "msl", "usim", "keypad", + "im", "memstk", "memc", "ssp1", + "camera", "ac97conf"; + clock-indices = < + CKEN_PWM0 CKEN_PWM1 CKEN_AC97 CKEN_SSP2 + CKEN_SSP3 CKEN_STUART CKEN_FFUART CKEN_BTUART + CKEN_I2S CKEN_OSTIMER CKEN_USBHOST CKEN_USB + CKEN_MMC CKEN_FICP CKEN_I2C CKEN_PWRI2C + CKEN_LCD CKEN_MSL CKEN_USIM CKEN_KEYPAD + CKEN_IM CKEN_MEMSTK 65 CKEN_SSP1 + CKEN_CAMERA CKEN_AC97CONF >; + }; + }; + }; diff --git a/include/dt-bindings/clock/pxa2xx-clock.h b/include/dt-bindings/clock/pxa2xx-clock.h new file mode 100644 index 0000000..5ffba58 --- /dev/null +++ b/include/dt-bindings/clock/pxa2xx-clock.h @@ -0,0 +1,45 @@ +/* + * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre + * Copyright (C) 2014 Robert Jarzmik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__ +#define __DT_BINDINGS_CLOCK_PXA2XX_H__ + +#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ +#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ +#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ +#define CKEN_MEMC (22) /* Memory Controller Clock Enable */ +#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ +#define CKEN_IM (20) /* Internal Memory Clock Enable */ +#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ +#define CKEN_USIM (18) /* USIM Unit Clock Enable */ +#define CKEN_MSL (17) /* MSL Unit Clock Enable */ +#define CKEN_LCD (16) /* LCD Unit Clock Enable */ +#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ +#define CKEN_I2C (14) /* I2C Unit Clock Enable */ +#define CKEN_FICP (13) /* FICP Unit Clock Enable */ +#define CKEN_MMC (12) /* MMC Unit Clock Enable */ +#define CKEN_USB (11) /* USB Unit Clock Enable */ +#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ +#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ +#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ +#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ +#define CKEN_I2S (8) /* I2S Unit Clock Enable */ +#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ +#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ +#define CKEN_STUART (5) /* STUART Unit Clock Enable */ +#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ +#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ +#define CKEN_SSP (3) /* SSP Unit Clock Enable */ +#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ +#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ +#define CKEN_PWM1 (1) /* PWM1 Clock Enable */ +#define CKEN_PWM0 (0) /* PWM0 Clock Enable */ + +#endif