From patchwork Mon Jun 30 16:03:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 4452641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6B37FBEEAA for ; Mon, 30 Jun 2014 16:07:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 763A0201EF for ; Mon, 30 Jun 2014 16:07:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B81C7202DD for ; Mon, 30 Jun 2014 16:07:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X1e4o-0003E4-EO; Mon, 30 Jun 2014 16:05:06 +0000 Received: from smtp.codeaurora.org ([198.145.11.231]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X1e4E-0002ad-6u for linux-arm-kernel@lists.infradead.org; Mon, 30 Jun 2014 16:04:31 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 4124F13F6DF; Mon, 30 Jun 2014 16:04:13 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 3028113F6E1; Mon, 30 Jun 2014 16:04:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: agross@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 77F9D13F6DF; Mon, 30 Jun 2014 16:04:12 +0000 (UTC) From: Andy Gross To: Felipe Balbi Subject: [Patch v7 3/3] usb: dwc3: qcom: Add device tree binding Date: Mon, 30 Jun 2014 11:03:53 -0500 Message-Id: <1404144233-17222-4-git-send-email-agross@codeaurora.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1404144233-17222-1-git-send-email-agross@codeaurora.org> References: <1404144233-17222-1-git-send-email-agross@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140630_090430_325215_471CCEB5 X-CRM114-Status: GOOD ( 13.41 ) X-Spam-Score: -0.0 (/) Cc: jackp@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, "Ivan T. Ivanov" , Kumar Gala , linux-arm-kernel@lists.infradead.org, Andy Gross X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Ivan T. Ivanov" QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys (SNPS) and HS, SS PHY's control and configuration registers. It could operate in device mode (SS, HS, FS) and host mode (SS, HS, FS, LS). Signed-off-by: Ivan T. Ivanov Signed-off-by: Andy Gross --- .../devicetree/bindings/usb/qcom,dwc3.txt | 104 ++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt new file mode 100644 index 0000000..105b6b7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt @@ -0,0 +1,104 @@ +Qualcomm SuperSpeed DWC3 USB SoC controller + + +QCOM DWC3 Highspeed USB PHY +======================== +Required properities: +- compatible: should contain "qcom,dwc3-hsphy"; +- reg: offset and length of the register set in the memory map +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Should contain the following: + "utmi" UTMI clock +- v1p8-supply: phandle to the regulator for the 1.8v supply to HSPHY. +- v3p3-supply: phandle to the regulator for the 3.3v supply to HSPHY. +- vbus-supply: phandle to the regulator for the vbus supply for host + mode. +- vddcx-supply: phandle to the regulator for the vdd supply for HSPHY + digital circuit operation. + +Optional clocks: + "xo" External reference clock + + +QCOM DWC3 Superspeed USB PHY +========================= +Required properities: +- compatible: should contain "qcom,dwc3-ssphy"; +- reg: offset and length of the register set in the memory map +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Should contain the following: + "ref" Reference clock used in host mode. +- v1p8-supply: phandle to the regulator for the 1.8v supply to HSPHY. +- vddcx-supply: phandle to the regulator for the vdd supply for HSPHY + digital circuit operation. + +Optional clocks: + "xo" External reference clock + +QCOM DWC3 controller wrapper +=========================== +Required properties: +- compatible: should contain "qcom,dwc3" +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Should contain the following: + "core" Master/Core clock, have to be >= 125 MHz for SS + operation and >= 60MHz for HS operation + +Optional clocks: + "iface" System bus AXI clock. Not present on all platforms + "sleep" Sleep clock, used when USB3 core goes into low + power mode (U3). + +Optional regulator: +- gdsc-supply: phandle to the regulator from globally distributed + switch controller + +Required child node: +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +Example device nodes: + + hs_phy_0: phy@110f8800 { + compatible = "qcom,dwc3-hsphy"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "utmi"; + + status = "disabled"; + }; + + ss_phy_0: phy@110f8830 { + compatible = "qcom,dwc3-ssphy"; + reg = <0x110f8830 0x30>; + + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + + status = "disabled"; + }; + + usb3_0: usb30@0 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + ranges; + + status = "disabled"; + + dwc3@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = <0 110 0x4>; + usb-phy = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + dr_mode = "host"; + }; + };