From patchwork Fri Jul 4 17:47:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 4482361 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 35E669F26C for ; Fri, 4 Jul 2014 17:49:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1566A20357 for ; Fri, 4 Jul 2014 17:49:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E028C20200 for ; Fri, 4 Jul 2014 17:49:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X37aM-0001va-2M; Fri, 04 Jul 2014 17:47:46 +0000 Received: from mail-pd0-x236.google.com ([2607:f8b0:400e:c02::236]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X37aH-0001fz-1N for linux-arm-kernel@lists.infradead.org; Fri, 04 Jul 2014 17:47:42 +0000 Received: by mail-pd0-f182.google.com with SMTP id y13so2233600pdi.13 for ; Fri, 04 Jul 2014 10:47:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=FwbbOzUi8abb8z5MZ/0IsX+oD076/NgiSJfsDptO840=; b=DdNGoMR3wlUZfCtxDhb/nlVkDYTZZkz0JKW70I/WhKhhQTJ+TXOyKzY2By/Do/fSEC Gb+Rd3PxhOZQUklb32F3I6M1S+HmzWiqJMyh0HEJcAemtcs4MpVxfAD/eujUN2ZZ5y0h xORl+5i5DDw92YTxnFD8jHZiwMAtukHHeAt00HGIGhpK4/iJ1FnTN9W13h1Y5f8pMRhZ p+vcATRegEuFI67JS1u4m02FWRYcdsXM6qBx7yhvK21TUbRli6N2L9AIdn5GeRD5P1CF xStvOZV5qn2ZntfQHQIXzYVxo6sfw/QqO86gWfefPTb9n6az85jm9EJIyRyqYAkot0g3 vNsg== X-Received: by 10.70.39.37 with SMTP id m5mr4233760pdk.131.1404496039763; Fri, 04 Jul 2014 10:47:19 -0700 (PDT) Received: from localhost.localdomain ([122.172.43.174]) by mx.google.com with ESMTPSA id xk1sm157496382pac.21.2014.07.04.10.47.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Jul 2014 10:47:19 -0700 (PDT) From: Abhilash Kesavan To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, nicolas.pitre@linaro.org, lorenzo.pieralisi@arm.com Subject: [PATCH v6] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420 Date: Fri, 4 Jul 2014 23:17:04 +0530 Message-Id: <1404496024-7113-1-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1404398818-6859-1-git-send-email-a.kesavan@samsung.com> References: <1404398818-6859-1-git-send-email-a.kesavan@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140704_104741_130136_C09721D5 X-CRM114-Status: GOOD ( 25.69 ) X-Spam-Score: -0.7 (/) Cc: abrestic@chromium.org, kesavan.abhilash@gmail.com, dianders@chromium.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use the MCPM layer to handle core suspend/resume on Exynos5420. Also, restore the entry address setup code post-resume. Signed-off-by: Abhilash Kesavan --- Changes in v2: - Made use of the MCPM suspend/powered_up call-backs Changes in v3: - Used the residency value to indicate the entered state Changes in v4: - Checked if MCPM has been enabled to prevent build error Changes in v5: - Removed the MCPM flags and just used a local flag to indicate that we are suspending. Changes in v6: - Read the SYS_PWR_REG value to decide if we are suspending the system. - Restore the SYS_PWR_REG value post-resume. - Modified the comments to reflect the first change. This has been tested both on an SMDK5420 and Peach Pit Chromebook on next-20140704. Nicolas' boot cluster CCI enablement patches are in linux-next now. Here are the dependencies (some of these patches did not apply cleanly): 1) Cleanup patches for mach-exynos http://comments.gmane.org/gmane.linux.kernel.samsung-soc/33772 2) PMU cleanup and refactoring for using DT https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg671625.html 3) Exynos5420 PMU/S2R Series http://comments.gmane.org/gmane.linux.kernel.samsung-soc/33898 4) Exynos5420 CPUIdle Series which populates MCPM suspend/powered_up call-backs. www.gossamer-threads.com/lists/linux/kernel/1945347 https://patchwork.kernel.org/patch/4357461/ 5) Exynos5420 MCPM cluster power down support http://www.spinics.net/lists/arm-kernel/msg339988.html 6) TPM reset mask patch http://www.spinics.net/lists/arm-kernel/msg341884.html arch/arm/mach-exynos/mcpm-exynos.c | 55 ++++++++++++++++++++++++++---------- arch/arm/mach-exynos/pm.c | 42 +++++++++++++++++++++++++-- 2 files changed, 80 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index 2dd51cc..26670e7 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -30,6 +31,8 @@ #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29) #define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30) +static void __iomem *ns_sram_base_addr; + /* * The common v7_exit_coherency_flush API could not be used because of the * Erratum 799270 workaround. This macro is the same as the common one (in @@ -129,11 +132,11 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster) * and can only be executed on processors like A15 and A7 that hit the cache * with the C bit clear in the SCTLR register. */ -static void exynos_power_down(void) +static void exynos_mcpm_power_down(u64 residency) { unsigned int mpidr, cpu, cluster; bool last_man = false, skip_wfi = false; - unsigned int cpunr; + unsigned int cpunr, temp; mpidr = read_cpuid_mpidr(); cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); @@ -150,7 +153,15 @@ static void exynos_power_down(void) BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP); cpu_use_count[cpu][cluster]--; if (cpu_use_count[cpu][cluster] == 0) { - exynos_cpu_power_down(cpunr); + /* + * Bypass power down for CPU0 during suspend. Check for + * the SYS_PWR_REG value to decide if we are suspending + * the system. + */ + temp = __raw_readl(pmu_base_addr + + EXYNOS5_ARM_CORE0_SYS_PWR_REG); + if ((cpu != 0) || ((temp & S5P_CORE_LOCAL_PWR_EN) != 0)) + exynos_cpu_power_down(cpunr); if (exynos_cluster_unused(cluster)) { exynos_cluster_power_down(cluster); @@ -209,6 +220,11 @@ static void exynos_power_down(void) /* Not dead at this point? Let our caller cope. */ } +static void exynos_power_down(void) +{ + exynos_mcpm_power_down(0); +} + static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster) { unsigned int tries = 100; @@ -250,11 +266,11 @@ static void exynos_suspend(u64 residency) { unsigned int mpidr, cpunr; - exynos_power_down(); + exynos_mcpm_power_down(residency); /* * Execution reaches here only if cpu did not power down. - * Hence roll back the changes done in exynos_power_down function. + * Hence roll back the changes done in exynos_mcpm_power_down function. * * CAUTION: "This function requires the stack data to be visible through * power down and can only be executed on processors like A15 and A7 @@ -319,10 +335,26 @@ static const struct of_device_id exynos_dt_mcpm_match[] = { {}, }; +static void exynos_mcpm_setup_entry_point(void) +{ + /* + * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr + * as part of secondary_cpu_start(). Let's redirect it to the + * mcpm_entry_point(). This is done during both secondary boot-up as + * well as system resume. + */ + __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */ + __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */ + __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8); +} + +static struct syscore_ops exynos_mcpm_syscore_ops = { + .resume = exynos_mcpm_setup_entry_point, +}; + static int __init exynos_mcpm_init(void) { struct device_node *node; - void __iomem *ns_sram_base_addr; unsigned int value, i; int ret; @@ -389,16 +421,9 @@ static int __init exynos_mcpm_init(void) __raw_writel(value, pmu_base_addr + EXYNOS_COMMON_OPTION(i)); } - /* - * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr - * as part of secondary_cpu_start(). Let's redirect it to the - * mcpm_entry_point(). - */ - __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */ - __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */ - __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8); + exynos_mcpm_setup_entry_point(); - iounmap(ns_sram_base_addr); + register_syscore_ops(&exynos_mcpm_syscore_ops); return ret; } diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 69cf678..d2751f4 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -24,6 +24,7 @@ #include #include +#include #include #include @@ -318,7 +319,10 @@ static void exynos_pm_prepare(void) /* ensure at least INFORM0 has the resume address */ - pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); + if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM)) + pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0); + else + pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); if (soc_is_exynos5420()) { tmp = __raw_readl(pmu_base_addr + EXYNOS5_ARM_L2_OPTION); @@ -408,6 +412,11 @@ static void exynos_pm_resume(void) unsigned int tmp; if (soc_is_exynos5420()) { + /* Restore the CPU0 low power state register */ + pmu_raw_writel( + __raw_readl(pmu_base_addr + EXYNOS5_ARM_CORE0_SYS_PWR_REG) | + S5P_CORE_LOCAL_PWR_EN, EXYNOS5_ARM_CORE0_SYS_PWR_REG); + /* Restore the sysram cpu state register */ __raw_writel(exynos5420_cpu_state, sysram_base_addr + EXYNOS5420_CPU_STATE); @@ -490,6 +499,28 @@ static struct syscore_ops exynos_pm_syscore_ops = { .resume = exynos_pm_resume, }; +static int notrace exynos_mcpm_cpu_suspend(unsigned long arg) +{ + /* MCPM works with HW CPU identifiers */ + unsigned int mpidr = read_cpuid_mpidr(); + unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + + __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE); + + mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); + + /* + * Residency value passed to mcpm_cpu_suspend back-end + * has to be given clear semantics. Set to 0 as a + * temporary value. + */ + mcpm_cpu_suspend(0); + + /* return value != 0 means failure */ + return 1; +} + /* * Suspend Ops */ @@ -517,10 +548,17 @@ static int exynos_suspend_enter(suspend_state_t state) flush_cache_all(); s3c_pm_check_store(); - ret = cpu_suspend(0, exynos_cpu_suspend); + /* Use the MCPM layer to suspend 5420 which is a multi-cluster SoC */ + if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM)) + ret = cpu_suspend(0, exynos_mcpm_cpu_suspend); + else + ret = cpu_suspend(0, exynos_cpu_suspend); if (ret) return ret; + if (soc_is_exynos5420() && IS_ENABLED(CONFIG_MCPM)) + mcpm_cpu_powered_up(); + s3c_pm_restore_uarts(); S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,