From patchwork Mon Jul 7 02:53:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 4492001 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D01419F36A for ; Mon, 7 Jul 2014 02:58:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C066E20225 for ; Mon, 7 Jul 2014 02:58:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DAD1E20222 for ; Mon, 7 Jul 2014 02:58:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X3z4l-0004fD-MM; Mon, 07 Jul 2014 02:54:43 +0000 Received: from mail-bl2lp0210.outbound.protection.outlook.com ([207.46.163.210] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X3z4i-0004eR-BE for linux-arm-kernel@lists.infradead.org; Mon, 07 Jul 2014 02:54:41 +0000 Received: from BLUPR03MB248.namprd03.prod.outlook.com (10.255.213.26) by BLUPR03MB518.namprd03.prod.outlook.com (10.141.80.143) with Microsoft SMTP Server (TLS) id 15.0.974.11; Mon, 7 Jul 2014 02:54:11 +0000 Received: from BY2PR03CA029.namprd03.prod.outlook.com (10.242.234.150) by BLUPR03MB248.namprd03.prod.outlook.com (10.255.213.26) with Microsoft SMTP Server (TLS) id 15.0.980.8; Mon, 7 Jul 2014 02:54:09 +0000 Received: from BL2FFO11FD028.protection.gbl (2a01:111:f400:7c09::125) by BY2PR03CA029.outlook.office365.com (2a01:111:e400:2c2c::22) with Microsoft SMTP Server (TLS) id 15.0.974.11 via Frontend Transport; Mon, 7 Jul 2014 02:54:08 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD028.mail.protection.outlook.com (10.173.161.107) with Microsoft SMTP Server (TLS) id 15.0.980.11 via Frontend Transport; Mon, 7 Jul 2014 02:54:08 +0000 Received: from dragon.ap.freescale.net ([10.192.185.244]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s672rwue007667; Sun, 6 Jul 2014 19:54:01 -0700 From: Shawn Guo To: , Fabio Estevam Subject: [PATCH] ARM: imx: fix shared gate clock Date: Mon, 7 Jul 2014 10:53:51 +0800 Message-ID: <1404701631-13870-1-git-send-email-shawn.guo@freescale.com> X-Mailer: git-send-email 1.8.3.2 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(199002)(189002)(229853001)(21056001)(50466002)(31966008)(77982001)(81156004)(50986999)(85852003)(87936001)(84676001)(87286001)(104166001)(83322001)(44976005)(19580395003)(106466001)(74502001)(76482001)(97736001)(19580405001)(4396001)(79102001)(105606002)(48376002)(80022001)(107046002)(6806004)(33646001)(50226001)(26826002)(62966002)(81542001)(81342001)(86362001)(93916002)(47776003)(64706001)(92726001)(68736004)(46102001)(74662001)(88136002)(89996001)(69596002)(99396002)(83072002)(85306003)(20776003)(36756003)(77156001)(92566001)(95666004)(102836001)(104016002); DIR:OUT; SFP:; SCL:1; SRVR:BLUPR03MB248; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 02652BD10A Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Shawn.Guo@freescale.com; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140706_195440_534550_437A1B0D X-CRM114-Status: GOOD ( 14.12 ) X-Spam-Score: -1.5 (-) Cc: Shawn Guo , linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, Nicolin Chen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by: Fabio Estevam Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo Tested-by: Fabio Estevam --- Fabio, Per my testing, it fixes the shared gate clock issue you reported. But I'd like to get your confirmation before I ask arm-soc folks to apply it for 3.16-rc. Shawn arch/arm/mach-imx/clk-gate2.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index 4ba587da89d2..84acdfd1d715 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -67,8 +67,12 @@ static void clk_gate2_disable(struct clk_hw *hw) spin_lock_irqsave(gate->lock, flags); - if (gate->share_count && --(*gate->share_count) > 0) - goto out; + if (gate->share_count) { + if (WARN_ON(*gate->share_count == 0)) + goto out; + else if (--(*gate->share_count) > 0) + goto out; + } reg = readl(gate->reg); reg &= ~(3 << gate->bit_idx); @@ -78,19 +82,26 @@ out: spin_unlock_irqrestore(gate->lock, flags); } -static int clk_gate2_is_enabled(struct clk_hw *hw) +static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) { - u32 reg; - struct clk_gate2 *gate = to_clk_gate2(hw); + u32 val = readl(reg); - reg = readl(gate->reg); - - if (((reg >> gate->bit_idx) & 1) == 1) + if (((val >> bit_idx) & 1) == 1) return 1; return 0; } +static int clk_gate2_is_enabled(struct clk_hw *hw) +{ + struct clk_gate2 *gate = to_clk_gate2(hw); + + if (gate->share_count) + return !!(*gate->share_count); + else + return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); +} + static struct clk_ops clk_gate2_ops = { .enable = clk_gate2_enable, .disable = clk_gate2_disable, @@ -116,6 +127,10 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, gate->bit_idx = bit_idx; gate->flags = clk_gate2_flags; gate->lock = lock; + + /* Initialize share_count per hardware state */ + if (share_count) + *share_count = clk_gate2_reg_is_enabled(reg, bit_idx) ? 1 : 0; gate->share_count = share_count; init.name = name;