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[86.181.29.22]) by mx.google.com with ESMTPSA id cd1sm103941088wjc.19.2014.07.09.08.08.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Jul 2014 08:08:06 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ulf.hansson@linaro.org, chris@printf.net, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com Subject: [PATCH v4 03/10] ARM: STi: DT: Add sdhci pins for stih416 Date: Wed, 9 Jul 2014 16:07:34 +0100 Message-Id: <1404918461-25390-4-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1404918461-25390-1-git-send-email-peter.griffin@linaro.org> References: <1404918461-25390-1-git-send-email-peter.griffin@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140709_080829_660779_E79D99E0 X-CRM114-Status: UNSURE ( 8.78 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) Cc: peter.griffin@linaro.org, linux-mmc@vger.kernel.org, peppe.cavallaro@st.com, lee.jones@linaro.org, devicetree@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the required pin config for both SDHCI controllers on the stih416 SoC. Signed-off-by: Giuseppe Cavallaro Signed-off-by: Peter Griffin Acked-by: Lee Jones Acked-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index ee6c119..01b5ad0 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -467,6 +467,45 @@ }; }; }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&PIO15 3 ALT4 IN>; + data4 = <&PIO16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&PIO16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&PIO17 1 ALT4 OUT>; + cd = <&PIO17 2 ALT4 IN>; + led = <&PIO17 3 ALT4 OUT>; + }; + }; + }; + mmc1 { + pinctrl_mmc1: mmc1 { + st,pins { + mmcclk = <&PIO15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO13 7 ALT3 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 1 ALT3 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 2 ALT3 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 3 ALT3 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 4 ALT3 BIDIR_PU BYPASS 0>; + data4 = <&PIO15 6 ALT3 BIDIR_PU BYPASS 0>; + data5 = <&PIO15 7 ALT3 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 0 ALT3 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 1 ALT3 BIDIR_PU BYPASS 0>; + pwr = <&PIO16 2 ALT3 OUT>; + nreset = <&PIO13 6 ALT3 OUT>; + }; + }; + }; }; pin-controller-fvdp-fe {