| Message ID | 1405022394-8311-2-git-send-email-boris.brezillon@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Boris, On 07/11/2014 03:59 AM, Boris BREZILLON wrote: > Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25) > and board specific timing configs. > > Atmel has two different HW designs for its CPU modules: the first one > (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors > and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up > resistor and PHYAD[1-2] to pull down resistors. > As a result, Ronetix design will have its PHY available at address 0x1 and > Embest design at 0x7. > By defining both phys we're letting the phy core detect the one actually > available on the MDIO bus. > > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> For this patch series, test OK on both Embest (sama5d34ek) and Ronetix (sama5d33ek). Tested-by: Bo Shen <voice.shen@atmel.com> > --- > > Florian, I dropped your Reviewed-by tag because this patch has slightly > changed. > > > arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi > index b0b1331..755369e 100644 > --- a/arch/arm/boot/dts/sama5d3xcm.dtsi > +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi > @@ -34,6 +34,36 @@ > > macb0: ethernet@f0028000 { > phy-mode = "rgmii"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethernet-phy@1 { > + reg = <0x1>; > + interrupt-parent = <&pioB>; > + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; > + txen-skew-ps = <800>; > + txc-skew-ps = <3000>; > + rxdv-skew-ps = <400>; > + rxc-skew-ps = <3000>; > + rxd0-skew-ps = <400>; > + rxd1-skew-ps = <400>; > + rxd2-skew-ps = <400>; > + rxd3-skew-ps = <400>; > + }; > + > + ethernet-phy@7 { > + reg = <0x7>; > + interrupt-parent = <&pioB>; > + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; > + txen-skew-ps = <800>; > + txc-skew-ps = <3000>; > + rxdv-skew-ps = <400>; > + rxc-skew-ps = <3000>; > + rxd0-skew-ps = <400>; > + rxd1-skew-ps = <400>; > + rxd2-skew-ps = <400>; > + rxd3-skew-ps = <400>; > + }; > }; > > pmc: pmc@fffffc00 { > Best Regards, Bo Shen
On 10/07/2014 21:59, Boris BREZILLON : > Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25) > and board specific timing configs. > > Atmel has two different HW designs for its CPU modules: the first one > (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors > and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up > resistor and PHYAD[1-2] to pull down resistors. > As a result, Ronetix design will have its PHY available at address 0x1 and > Embest design at 0x7. > By defining both phys we're letting the phy core detect the one actually > available on the MDIO bus. > > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> > --- > > Florian, I dropped your Reviewed-by tag because this patch has slightly > changed. Hi Florian, I would like to have your Ack on this one as we discussed this solution with you. Thanks, bye, > arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi > index b0b1331..755369e 100644 > --- a/arch/arm/boot/dts/sama5d3xcm.dtsi > +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi > @@ -34,6 +34,36 @@ > > macb0: ethernet@f0028000 { > phy-mode = "rgmii"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethernet-phy@1 { > + reg = <0x1>; > + interrupt-parent = <&pioB>; > + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; > + txen-skew-ps = <800>; > + txc-skew-ps = <3000>; > + rxdv-skew-ps = <400>; > + rxc-skew-ps = <3000>; > + rxd0-skew-ps = <400>; > + rxd1-skew-ps = <400>; > + rxd2-skew-ps = <400>; > + rxd3-skew-ps = <400>; > + }; > + > + ethernet-phy@7 { > + reg = <0x7>; > + interrupt-parent = <&pioB>; > + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; > + txen-skew-ps = <800>; > + txc-skew-ps = <3000>; > + rxdv-skew-ps = <400>; > + rxc-skew-ps = <3000>; > + rxd0-skew-ps = <400>; > + rxd1-skew-ps = <400>; > + rxd2-skew-ps = <400>; > + rxd3-skew-ps = <400>; > + }; > }; > > pmc: pmc@fffffc00 { >
2014-07-18 7:21 GMT-07:00 Nicolas Ferre <nicolas.ferre@atmel.com>: > On 10/07/2014 21:59, Boris BREZILLON : >> Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25) >> and board specific timing configs. >> >> Atmel has two different HW designs for its CPU modules: the first one >> (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors >> and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up >> resistor and PHYAD[1-2] to pull down resistors. >> As a result, Ronetix design will have its PHY available at address 0x1 and >> Embest design at 0x7. >> By defining both phys we're letting the phy core detect the one actually >> available on the MDIO bus. >> >> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> >> --- >> >> Florian, I dropped your Reviewed-by tag because this patch has slightly >> changed. > > Hi Florian, > > I would like to have your Ack on this one as we discussed this solution > with you. Acked-by: Florian Fainelli <f.fainelli@gmail.com> > > Thanks, bye, > > >> arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++ >> 1 file changed, 30 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi >> index b0b1331..755369e 100644 >> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi >> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi >> @@ -34,6 +34,36 @@ >> >> macb0: ethernet@f0028000 { >> phy-mode = "rgmii"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + ethernet-phy@1 { >> + reg = <0x1>; >> + interrupt-parent = <&pioB>; >> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; >> + txen-skew-ps = <800>; >> + txc-skew-ps = <3000>; >> + rxdv-skew-ps = <400>; >> + rxc-skew-ps = <3000>; >> + rxd0-skew-ps = <400>; >> + rxd1-skew-ps = <400>; >> + rxd2-skew-ps = <400>; >> + rxd3-skew-ps = <400>; >> + }; >> + >> + ethernet-phy@7 { >> + reg = <0x7>; >> + interrupt-parent = <&pioB>; >> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; >> + txen-skew-ps = <800>; >> + txc-skew-ps = <3000>; >> + rxdv-skew-ps = <400>; >> + rxc-skew-ps = <3000>; >> + rxd0-skew-ps = <400>; >> + rxd1-skew-ps = <400>; >> + rxd2-skew-ps = <400>; >> + rxd3-skew-ps = <400>; >> + }; >> }; >> >> pmc: pmc@fffffc00 { >> > > > -- > Nicolas Ferre
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index b0b1331..755369e 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -34,6 +34,36 @@ macb0: ethernet@f0028000 { phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; }; pmc: pmc@fffffc00 {
Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25) and board specific timing configs. Atmel has two different HW designs for its CPU modules: the first one (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up resistor and PHYAD[1-2] to pull down resistors. As a result, Ronetix design will have its PHY available at address 0x1 and Embest design at 0x7. By defining both phys we're letting the phy core detect the one actually available on the MDIO bus. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> --- Florian, I dropped your Reviewed-by tag because this patch has slightly changed. arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)