From patchwork Fri Jul 11 20:36:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 4537321 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 912009F333 for ; Fri, 11 Jul 2014 20:41:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5F99F20115 for ; Fri, 11 Jul 2014 20:41:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D07C2202EC for ; Fri, 11 Jul 2014 20:41:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X5haV-0008PL-KT; Fri, 11 Jul 2014 20:38:35 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X5hZz-0008D4-C5 for linux-arm-kernel@lists.infradead.org; Fri, 11 Jul 2014 20:38:05 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6BKadoZ004660; Fri, 11 Jul 2014 15:36:39 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6BKacRA020112; Fri, 11 Jul 2014 15:36:38 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Fri, 11 Jul 2014 15:36:38 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6BKaWuf016223; Fri, 11 Jul 2014 15:36:37 -0500 From: Murali Karicheri To: , , Subject: [PATCH v4 4/6] PCI: designware: enhance dw core driver to support keystone PCI host controller Date: Fri, 11 Jul 2014 16:36:33 -0400 Message-ID: <1405110995-24676-5-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405110995-24676-1-git-send-email-m-karicheri2@ti.com> References: <1405110995-24676-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140711_133803_519261_EF90C02A X-CRM114-Status: GOOD ( 16.63 ) X-Spam-Score: -5.7 (-----) Cc: Richard Zhu , Pratyush Anand , Marek Vasut , Russell King , Pawel Moll , Arnd Bergmann , Ian Campbell , Mohit Kumar , Jingoo Han , Rob Herring , Kishon Vijay Abraham I , Bjorn Helgaas , Murali Karicheri , Randy Dunlap , Kumar Gala , Grant Likely , Mark Rutland X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add API dw_pcie_v3_65_host_init() to support host controller initialization for keystone PCI driver. The keystone PCI uses v3.65 version of the DW hardware identified by compatibility string "dw,snps-pcie-v3.65". This allow for different treatment for this version of the h/w during host initialization. Key differences in v3.65 DW h/w are 1. No ATU support 2. Legacy and MSI irq functions are implemented in application register space 3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side. So a msi irq chip is needed and the irq domain ops ptr is passed in dw_pcie_v3_65_host_init() to allow re-use of common MSI code in dw core. The keystone PCI host controller requires a modified pci scan function to allow setup BAR0 for EP's access to MSI_IRQ register in application register to raise MSI irq. So a ptr to pci hw ops struct is passed to the host init code. keystone PCI controller re-uses the DW Core driver code wherever there is common functionality. So this patch makes these functions global and added their prototypes in pcie-designware.h to allow re-use on keystone. Signed-off-by: Murali Karicheri Acked-by: Santosh Shilimkar CC: Russell King CC: Grant Likely CC: Rob Herring CC: Mohit Kumar CC: Jingoo Han CC: Bjorn Helgaas CC: Pratyush Anand CC: Richard Zhu CC: Kishon Vijay Abraham I CC: Marek Vasut CC: Arnd Bergmann CC: Pawel Moll CC: Mark Rutland CC: Ian Campbell CC: Kumar Gala CC: Randy Dunlap CC: Grant Likely --- .../devicetree/bindings/pci/designware-pcie.txt | 2 + drivers/pci/host/pcie-designware.c | 39 ++++++++++++++++++-- drivers/pci/host/pcie-designware.h | 7 ++++ 3 files changed, 44 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index d0d15ee..0cb10c0 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -2,6 +2,8 @@ Required properties: - compatible: should contain "snps,dw-pcie" to identify the core. + Additionally contains "dw,snps-pcie-v3.65" to identify v3.65 version of the DW + hardware. - #address-cells: set to <3> - #size-cells: set to <2> - device_type: set to "pci" diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index c11e4de..4dcbebe 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -556,6 +556,37 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp, return 0; } +int __init dw_pcie_v3_65_host_init(struct pcie_port *pp, struct hw_pci *hw, + struct device_node *msi_irqc_np, + const struct irq_domain_ops *msi_irq_ops) +{ + int ret = -EINVAL; + + /* check if compatible with v3.65 DW h/w */ + if (!of_device_is_compatible(pp->dev->of_node, "dw,snps-pcie-v3.65")) { + dev_err(pp->dev, + "PCI Controller not compatible with v3.65 DW h/w\n"); + goto out; + } + pp->version = DW_HW_V3_65; + + /* v3.65 PCI controller is expected to provide its own PCI h/w ops */ + if (!hw || !msi_irq_ops) { + dev_err(pp->dev, + "v3.65 PCI Controllers doesn't provide %s\n", + (hw == NULL) ? "PCI hw ops" : "PCI MSI irq domain ops"); + goto out; + } + + ret = dw_pcie_msi_host_init(pp, msi_irqc_np, msi_irq_ops); + if (ret) + goto out; + + ret = dw_pcie_common_host_init(pp, hw); +out: + return ret; +} + int __init dw_pcie_host_init(struct pcie_port *pp) { int ret; @@ -763,7 +794,7 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) +int dw_pcie_setup(int nr, struct pci_sys_data *sys) { struct pcie_port *pp; @@ -786,7 +817,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) return 1; } -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; struct pcie_port *pp = sys_to_pcie(sys); @@ -803,7 +834,7 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) return bus; } -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); int irq; @@ -815,7 +846,7 @@ static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -static void dw_pcie_add_bus(struct pci_bus *bus) +void dw_pcie_add_bus(struct pci_bus *bus) { if (IS_ENABLED(CONFIG_PCI_MSI)) { struct pcie_port *pp = sys_to_pcie(bus->sysdata); diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index db0260f..2681826 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -81,4 +81,11 @@ void dw_pcie_msi_init(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); +int dw_pcie_v3_65_host_init(struct pcie_port *pp, struct hw_pci *hw, + struct device_node *msi_irqc_np, + const struct irq_domain_ops *msi_irq_ops); +int dw_pcie_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys); +void dw_pcie_add_bus(struct pci_bus *bus); +int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); #endif /* _PCIE_DESIGNWARE_H */