From patchwork Mon Jul 14 22:06:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonny Rao X-Patchwork-Id: 4549901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D441C9F2F4 for ; Mon, 14 Jul 2014 22:09:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D93132012F for ; Mon, 14 Jul 2014 22:09:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CF51920108 for ; Mon, 14 Jul 2014 22:09:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X6oOn-0000tj-M1; Mon, 14 Jul 2014 22:07:05 +0000 Received: from mail-pd0-f201.google.com ([209.85.192.201]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X6oOk-0000qj-B1 for linux-arm-kernel@lists.infradead.org; Mon, 14 Jul 2014 22:07:03 +0000 Received: by mail-pd0-f201.google.com with SMTP id v10so1054853pde.2 for ; Mon, 14 Jul 2014 15:06:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iAAHgUYfVdAJva8s5Z1d9sZgShp5ahSsrCrlUjvlX9Q=; b=ZqEmd3G5rzyPEGGf9k36Ru79MX8iD96IWgwbGYR1BTEPXVIl4vdU5gSYiDQodUXVqd D8bqsosz+WzkzDgSbDXXcCW4gyqZiCT9OEzLay9BYPTZK+r9SEEkvOnuqq00SuhjN2+u d/mdMYjpcJTDImowBYkhL6rdwbwxsGYdrIZPVpWbiVzJFk3sWwiiNnMeESiprhyJLFxE JfinK3omDlAeiQEgebU7BPglCttrHndSPILUJpxq3rUuUOyf4MyDyJQ5Vg+I7dfDCxJl FANBQDupmoqJ1r1tbrNyvUAAuXQEU+yAhe75gGz8+nlrt1G8DdC1RhGnPK5TR4bZt+st QUAQ== X-Gm-Message-State: ALoCoQltc/SWphP8FPGg0vXduckWEUOYf68q9uk1ev3pSL5+Ko0asQwnNpG4wIOGD/9IQm88U0H1 X-Received: by 10.66.235.66 with SMTP id uk2mr4686699pac.39.1405375600204; Mon, 14 Jul 2014 15:06:40 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id o69si832292yhp.6.2014.07.14.15.06.40 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Jul 2014 15:06:40 -0700 (PDT) Received: from sonnyrao.mtv.corp.google.com (sonnyrao.mtv.corp.google.com [172.22.72.76]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id EE68831C40F; Mon, 14 Jul 2014 15:06:39 -0700 (PDT) Received: by sonnyrao.mtv.corp.google.com (Postfix, from userid 129445) id 9B8A4A0C97; Mon, 14 Jul 2014 15:06:39 -0700 (PDT) From: Sonny Rao To: linux-mmc@vger.kernel.org Subject: [PATCHv6] mmc: dw_mmc: change to use recommended reset procedure Date: Mon, 14 Jul 2014 15:06:31 -0700 Message-Id: <1405375591-13409-1-git-send-email-sonnyrao@chromium.org> X-Mailer: git-send-email 2.0.0.526.g5318336 In-Reply-To: <53C37029.20600@samsung.com> References: <53C37029.20600@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140714_150702_427871_F3E64EA0 X-CRM114-Status: GOOD ( 23.35 ) X-Spam-Score: -0.0 (/) Cc: Yuvaraj Kumar C D , linux-samsung-soc@vger.kernel.org, grundler@chromium.org, t.figa@samsung.com, joshi@samsung.com, dianders@chromium.org, jh80.chung@samsung.com, tgih.jun@samsung.com, kgene.kim@samsung.com, cjb@laptop.org, Sonny Rao , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch changes the fifo reset code to follow the reset procedure outlined in the documentation of Synopsys Mobile storage host databook. Signed-off-by: Sonny Rao Signed-off-by: Yuvaraj Kumar C D Acked-by: Seungwon Jeon --- v2: Add Generic DMA support per the documentation, move interrupt clear before wait make the test for DMA host->use_dma rather than host->using_dma add proper return values (although it appears no caller checks) v3: rename fifo reset function, and change callers use this combined reset function in dw_mci_resume() just one caller left (probe), so get rid of dw_mci_ctrl_all_reset() use DMA reset bit for all systems which use DMA remove extra IDMAC reset in dw_mci_work_routine_card() do CIU clock update in error path, if CIU reset cleared v4: remove comment about FIFO reset in dw_mci_work_routine_card() move down error message when control reset clears but others don't and clarify the error stating that we will still update clocks make flags for all reset bits a macro v5: don't use dw_mci_reset() in dw_mci_resume() and instead match what is done in dw_mci_probe() and don't force inline dw_mci_resume() v6: add newlines to dev_err() messages --- drivers/mmc/host/dw_mmc.c | 86 ++++++++++++++++++++++++++++++++++------------- drivers/mmc/host/dw_mmc.h | 5 +++ 2 files changed, 68 insertions(+), 23 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 55cd110..0c0aecb 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -111,8 +111,7 @@ static const u8 tuning_blk_pattern_8bit[] = { 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, }; -static inline bool dw_mci_fifo_reset(struct dw_mci *host); -static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host); +static bool dw_mci_reset(struct dw_mci *host); #if defined(CONFIG_DEBUG_FS) static int dw_mci_req_show(struct seq_file *s, void *v) @@ -1254,7 +1253,7 @@ static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) * After an error, there may be data lingering * in the FIFO */ - dw_mci_fifo_reset(host); + dw_mci_reset(host); } else { data->bytes_xfered = data->blocks * data->blksz; data->error = 0; @@ -1371,7 +1370,7 @@ static void dw_mci_tasklet_func(unsigned long priv) /* CMD error in data command */ if (mrq->cmd->error && mrq->data) - dw_mci_fifo_reset(host); + dw_mci_reset(host); host->cmd = NULL; host->data = NULL; @@ -1982,14 +1981,8 @@ static void dw_mci_work_routine_card(struct work_struct *work) } /* Power down slot */ - if (present == 0) { - /* Clear down the FIFO */ - dw_mci_fifo_reset(host); -#ifdef CONFIG_MMC_DW_IDMAC - dw_mci_idmac_reset(host); -#endif - - } + if (present == 0) + dw_mci_reset(host); spin_unlock_bh(&host->lock); @@ -2323,8 +2316,11 @@ static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) return false; } -static inline bool dw_mci_fifo_reset(struct dw_mci *host) +static bool dw_mci_reset(struct dw_mci *host) { + u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; + bool ret = false; + /* * Reseting generates a block interrupt, hence setting * the scatter-gather pointer to NULL. @@ -2334,15 +2330,59 @@ static inline bool dw_mci_fifo_reset(struct dw_mci *host) host->sg = NULL; } - return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET); -} + if (host->use_dma) + flags |= SDMMC_CTRL_DMA_RESET; -static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host) -{ - return dw_mci_ctrl_reset(host, - SDMMC_CTRL_FIFO_RESET | - SDMMC_CTRL_RESET | - SDMMC_CTRL_DMA_RESET); + if (dw_mci_ctrl_reset(host, flags)) { + /* + * In all cases we clear the RAWINTS register to clear any + * interrupts. + */ + mci_writel(host, RINTSTS, 0xFFFFFFFF); + + /* if using dma we wait for dma_req to clear */ + if (host->use_dma) { + unsigned long timeout = jiffies + msecs_to_jiffies(500); + u32 status; + do { + status = mci_readl(host, STATUS); + if (!(status & SDMMC_STATUS_DMA_REQ)) + break; + cpu_relax(); + } while (time_before(jiffies, timeout)); + + if (status & SDMMC_STATUS_DMA_REQ) { + dev_err(host->dev, + "%s: Timeout waiting for dma_req to " + "clear during reset\n", __func__); + goto ciu_out; + } + + /* when using DMA next we reset the fifo again */ + if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) + goto ciu_out; + } + } else { + /* if the controller reset bit did clear, then set clock regs */ + if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { + dev_err(host->dev, "%s: fifo/dma reset bits didn't " + "clear but ciu was reset, doing clock update\n", + __func__); + goto ciu_out; + } + } + + if (IS_ENABLED(CONFIG_MMC_DW_IDMAC)) + /* It is also recommended that we reset and reprogram idmac */ + dw_mci_idmac_reset(host); + + ret = true; + +ciu_out: + /* After a CTRL reset we need to have CIU set clock registers */ + mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); + + return ret; } #ifdef CONFIG_OF @@ -2555,7 +2595,7 @@ int dw_mci_probe(struct dw_mci *host) } /* Reset all blocks */ - if (!dw_mci_ctrl_all_reset(host)) + if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) return -ENODEV; host->dma_ops = host->pdata->dma_ops; @@ -2744,7 +2784,7 @@ int dw_mci_resume(struct dw_mci *host) } } - if (!dw_mci_ctrl_all_reset(host)) { + if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { ret = -ENODEV; return ret; } diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 6bf24ab..9ab8ccd 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -129,6 +129,7 @@ #define SDMMC_CMD_INDX(n) ((n) & 0x1F) /* Status register defines */ #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) +#define SDMMC_STATUS_DMA_REQ BIT(31) /* FIFOTH register defines */ #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ ((r) & 0xFFF) << 16 | \ @@ -150,6 +151,10 @@ /* Card read threshold */ #define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x)) +/* All ctrl reset bits */ +#define SDMMC_CTRL_ALL_RESET_FLAGS \ + (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) + /* Register access macros */ #define mci_readl(dev, reg) \ __raw_readl((dev)->regs + SDMMC_##reg)