From patchwork Tue Jul 15 15:24:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 4555261 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E42809F1D6 for ; Tue, 15 Jul 2014 15:31:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2389E20122 for ; Tue, 15 Jul 2014 15:31:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71B71200EC for ; Tue, 15 Jul 2014 15:31:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X74fN-0000wc-3B; Tue, 15 Jul 2014 15:29:17 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X74cw-0002oW-8b for linux-arm-kernel@lists.infradead.org; Tue, 15 Jul 2014 15:26:46 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 15 Jul 2014 08:25:33 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 15 Jul 2014 08:15:05 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 15 Jul 2014 08:15:05 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.342.0; Tue, 15 Jul 2014 08:26:19 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Tue, 15 Jul 2014 08:26:19 -0700 Received: from tbergstrom-lnx.nvidia.com (tbergstrom-lnx.nvidia.com [10.21.24.170]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id s6FFOve3027110; Tue, 15 Jul 2014 08:26:15 -0700 (PDT) From: Peter De Schrijver To: Peter De Schrijver Subject: [PATCH 4/6] clk: tegra: add nvidia,tegra132-ccplex-clk binding Date: Tue, 15 Jul 2014 18:24:34 +0300 Message-ID: <1405437890-6468-5-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty In-Reply-To: <1405437890-6468-1-git-send-email-pdeschrijver@nvidia.com> References: <1405437890-6468-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140715_082646_354041_DA773679 X-CRM114-Status: GOOD ( 13.51 ) X-Spam-Score: -0.0 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Prashant Gaikwad , Russell King , Pawel Moll , Stephen Warren , Ian Campbell , Joseph Lo , linux-kernel@vger.kernel.org, Rob Herring , Thierry Reding , Tuomas Tynkkynen , Kumar Gala , linux-tegra@vger.kernel.org, Mike Turquette , Alexandre Courbot , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra132 has a few new clocks for the CPU complex (ccplex). Signed-off-by: Peter De Schrijver --- .../bindings/clock/nvidia,tegra132-ccplex-clk.txt | 27 ++++++++++++++++++++ include/dt-bindings/clock/tegra132-ccplex.h | 12 +++++++++ 2 files changed, 39 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra132-ccplex-clk.txt create mode 100644 include/dt-bindings/clock/tegra132-ccplex.h diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra132-ccplex-clk.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra132-ccplex-clk.txt new file mode 100644 index 0000000..1441e36 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra132-ccplex-clk.txt @@ -0,0 +1,27 @@ +NVIDIA Tegra132 ccplex clocks + +This binding uses the common clock binding: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +The Tegra132 ccplex clock module on Tegra132 is the HW module responsible +for the ccplex related clocks. + +Required properties : +- compatible : Should be "nvidia,tegra132-ccplex-clk" +- reg : Should contain ccplex clock registers location and length +- #clock-cells : Should be 1. + In clock consumers, this cell represents the clock ID exposed by the + ccplex clock module. The assignments may be found in header file + . + +Example SoC include file: + +/ { + ccplex-clock@0,70040000 { + compatible = "nvidia,tegra132-ccplex-clk"; + reg = <0x0 0x70040000 0x0 0x1000>; + status = "okay"; + #clock-cells = <1>; + }; + +}; diff --git a/include/dt-bindings/clock/tegra132-ccplex.h b/include/dt-bindings/clock/tegra132-ccplex.h new file mode 100644 index 0000000..58ea190 --- /dev/null +++ b/include/dt-bindings/clock/tegra132-ccplex.h @@ -0,0 +1,12 @@ +/* + * This header provides constants for the binding nvidia,tegra132-ccplex-clk + */ + +#ifndef __DT_BINDINGS_CLOCK_TEGRA132_CCPLEX_H +#define __DT_BINDINGS_CLOCK_TEGRA132_CCPLEX_H + +#define TEGRA132_CCPLEX_CCLK_G 1 +#define TEGRA132_PLL_X 2 +#define TEGRA132_CCPLEX_CLK_MAX 3 + +#endif