From patchwork Tue Jul 15 15:24:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 4555271 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0BB4FC0514 for ; Tue, 15 Jul 2014 15:31:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6649D20122 for ; Tue, 15 Jul 2014 15:31:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 687FC200EC for ; Tue, 15 Jul 2014 15:31:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X74fc-0001RK-1W; Tue, 15 Jul 2014 15:29:32 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X74dA-00045e-DL for linux-arm-kernel@lists.infradead.org; Tue, 15 Jul 2014 15:27:00 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 15 Jul 2014 08:25:51 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 15 Jul 2014 08:15:23 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 15 Jul 2014 08:15:23 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.342.0; Tue, 15 Jul 2014 08:26:38 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Tue, 15 Jul 2014 08:26:38 -0700 Received: from tbergstrom-lnx.nvidia.com (tbergstrom-lnx.nvidia.com [10.21.24.170]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id s6FFOve4027110; Tue, 15 Jul 2014 08:26:34 -0700 (PDT) From: Peter De Schrijver To: Peter De Schrijver Subject: [PATCH 5/6] clk: tegra: Add support for Tegra132 CAR clocks Date: Tue, 15 Jul 2014 18:24:35 +0300 Message-ID: <1405437890-6468-6-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty In-Reply-To: <1405437890-6468-1-git-send-email-pdeschrijver@nvidia.com> References: <1405437890-6468-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140715_082700_492035_4C7195CE X-CRM114-Status: GOOD ( 16.50 ) X-Spam-Score: -0.0 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Prashant Gaikwad , Russell King , Pawel Moll , Stephen Warren , Ian Campbell , Joseph Lo , linux-kernel@vger.kernel.org, Rob Herring , Thierry Reding , Tuomas Tynkkynen , Kumar Gala , linux-tegra@vger.kernel.org, Mike Turquette , Alexandre Courbot , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This patch deals with the small differences. --- I'm not entirely sure why the soc_therm clock needs to be enabled on Tegra132, but turning it off results in a system hang. I presume this might be because of fastboot initializing soc_therm. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra124.c | 32 ++++++++++++++++++++++++++++++++ 1 files changed, 32 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 80efe51..b857aab 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1369,6 +1369,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { {TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0}, {TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0}, {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0}, + {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0}, /* This MUST be the last entry. */ {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, }; @@ -1378,9 +1379,25 @@ static void __init tegra124_clock_apply_init_table(void) tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX); } +enum { + TEGRA124_CLK, + TEGRA132_CLK, +}; + +static const struct of_device_id tegra_clock_of_match[] = { + { .compatible = "nvidia,tegra124-car", .data = (void *)TEGRA124_CLK }, + { .compatible = "nvidia,tegra132-car", .data = (void *)TEGRA132_CLK }, + {}, +}; + static void __init tegra124_clock_init(struct device_node *np) { struct device_node *node; + const struct of_device_id *match; + uintptr_t id; + + match = of_match_node(tegra_clock_of_match, np); + id = (uintptr_t)match->data; clk_base = of_iomap(np, 0); if (!clk_base) { @@ -1416,6 +1433,20 @@ static void __init tegra124_clock_init(struct device_node *np) tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params); tegra_pmc_clk_init(pmc_base, tegra124_clks); + if (id == TEGRA132_CLK) { + int i; + + tegra124_clks[tegra_clk_cclk_g].present = false; + tegra124_clks[tegra_clk_cclk_lp].present = false; + tegra124_clks[tegra_clk_pll_x].present = false; + tegra124_clks[tegra_clk_pll_x_out0].present = false; + + /* Tegra132 requires the soc_therm clock to be always on */ + for (i = 0; i < ARRAY_SIZE(init_table); i++) { + if (init_table[i].clk_id == TEGRA124_CLK_SOC_THERM) + init_table[i].state = 1; + } + } tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks, &pll_x_params); tegra_add_of_provider(np); @@ -1426,3 +1457,4 @@ static void __init tegra124_clock_init(struct device_node *np) tegra_cpu_car_ops = &tegra124_cpu_car_ops; } CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init); +CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra124_clock_init);