From patchwork Mon Jul 21 16:48:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 4597461 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6ECA7C0514 for ; Mon, 21 Jul 2014 16:52:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 880AD20109 for ; Mon, 21 Jul 2014 16:52:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F0E5200D5 for ; Mon, 21 Jul 2014 16:52:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X9Gn8-0001Vy-VI; Mon, 21 Jul 2014 16:50:22 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X9GmZ-0008Sp-KR for linux-arm-kernel@lists.infradead.org; Mon, 21 Jul 2014 16:49:48 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 607CD7FD; Mon, 21 Jul 2014 18:49:30 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (unknown [190.2.108.81]) by mail.free-electrons.com (Postfix) with ESMTPSA id A5CBC7A0; Mon, 21 Jul 2014 18:49:27 +0200 (CEST) From: Ezequiel Garcia To: , Subject: [PATCH 2/6] net: mvpp2: Enable proper PHY polling and fix port functionality Date: Mon, 21 Jul 2014 13:48:12 -0300 Message-Id: <1405961296-5846-3-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1405961296-5846-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1405961296-5846-1-git-send-email-ezequiel.garcia@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140721_094947_968255_77396E3B X-CRM114-Status: GOOD ( 15.16 ) X-Spam-Score: 1.0 (+) Cc: Thomas Petazzoni , Lior Amsalem , Jason Cooper , Tawfik Bayouk , Gregory Clement , Marcin Wojtas , David Miller X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marcin Wojtas Currently, the network interfaces that are not configured by the bootloader (using e.g. tftp or ping) can detect the link status but are unable to transmit data. The network controller has a functionality that allows the hardware to continuously poll the PHY and directly update the MAC configuration accordingly (speed, duplex, etc.). However, this doesn't work well with phylib's software-based polling and updating MAC configuration in the driver's callback. This commit fixes this issue by: 1. Setting MVPP2_PHY_AN_STOP_SMI0_MASK in MVPP2_PHY_AN_CFG0_REG in mvpp2_init(), which disables the harware polling feature. 2. Disabling MVPP2_GMAC_PCS_ENABLE_MASK bit in MVPP2_GMAC_CTRL_2_REG in mvpp2_port_mii_set() for port types other than SGMII. Signed-off-by: Marcin Wojtas --- drivers/net/ethernet/marvell/mvpp2.c | 40 ++++++++++++++++++++++++++++-------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 8eac438..aa139df 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -248,6 +248,8 @@ /* LMS registers */ #define MVPP2_SRC_ADDR_MIDDLE 0x24 #define MVPP2_SRC_ADDR_HIGH 0x28 +#define MVPP2_PHY_AN_CFG0_REG 0x34 +#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) #define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * \ 0x400 + (port) * 0x400) #define MVPP2_MIB_LATE_COLLISION 0x7c @@ -278,6 +280,7 @@ #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) #define MVPP2_GMAC_AN_SPEED_EN BIT(7) +#define MVPP2_GMAC_FC_ADV_EN BIT(9) #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c @@ -3809,16 +3812,30 @@ static void mvpp2_interrupts_unmask(void *arg) static void mvpp2_port_mii_set(struct mvpp2_port *port) { - u32 reg, val = 0; + u32 val; - if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) - val = MVPP2_GMAC_PCS_ENABLE_MASK | - MVPP2_GMAC_INBAND_AN_MASK; - else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII) - val = MVPP2_GMAC_PORT_RGMII_MASK; + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); + + switch (port->phy_interface) { + case PHY_INTERFACE_MODE_SGMII: + val |= MVPP2_GMAC_INBAND_AN_MASK; + break; + case PHY_INTERFACE_MODE_RGMII: + val |= MVPP2_GMAC_PORT_RGMII_MASK; + default: + val &= ~MVPP2_GMAC_PCS_ENABLE_MASK; + } + + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); +} - reg = readl(port->base + MVPP2_GMAC_CTRL_2_REG); - writel(reg | val, port->base + MVPP2_GMAC_CTRL_2_REG); +static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val |= MVPP2_GMAC_FC_ADV_EN; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); } static void mvpp2_port_enable(struct mvpp2_port *port) @@ -5877,6 +5894,7 @@ static void mvpp2_port_power_up(struct mvpp2_port *port) { mvpp2_port_mii_set(port); mvpp2_port_periodic_xon_disable(port); + mvpp2_port_fc_adv_enable(port); mvpp2_port_reset(port); } @@ -6198,6 +6216,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) { const struct mbus_dram_target_info *dram_target_info; int err, i; + u32 val; /* Checks for hardware constraints */ if (rxq_number % 4 || (rxq_number > MVPP2_MAX_RXQ) || @@ -6211,6 +6230,11 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) if (dram_target_info) mvpp2_conf_mbus_windows(dram_target_info, priv); + /* Disable HW PHY polling */ + val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); + val |= MVPP2_PHY_AN_STOP_SMI0_MASK; + writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); + /* Allocate and initialize aggregated TXQs */ priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(), sizeof(struct mvpp2_tx_queue),