From patchwork Mon Jul 28 22:55:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geoff Levand X-Patchwork-Id: 4637871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 929E3C0338 for ; Mon, 28 Jul 2014 22:58:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CFE6F2018E for ; Mon, 28 Jul 2014 22:58:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D7D8C2018B for ; Mon, 28 Jul 2014 22:58:06 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBtpv-0008E5-BB; Mon, 28 Jul 2014 22:56:07 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBtpt-0008Dd-34 for linux-arm-kernel@bombadil.infradead.org; Mon, 28 Jul 2014 22:56:05 +0000 Received: from 107-1-141-74-ip-static.hfc.comcastbusiness.net ([107.1.141.74] helo=[192.168.254.170]) by casper.infradead.org with esmtpsa (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBtpq-00073P-I3; Mon, 28 Jul 2014 22:56:02 +0000 Message-ID: <1406588159.28348.41.camel@smoke> Subject: [PATCH] arm64: Fix UP build warning in gic-v3 From: Geoff Levand To: Marc Zyngier Date: Mon, 28 Jul 2014 15:55:59 -0700 X-Mailer: Evolution 3.10.4-0ubuntu1 Mime-Version: 1.0 Cc: "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The static routines gic_write_sgi1r() and gic_peek_irq() are only used for SMP builds, so move those two routines to within the defined(CONFIG_SMP) preprocessor conditional. Fixes build warnings like these when CONFIG_SMP=n: drivers/irqchip/irq-gic-v3.c: warning: ‘gic_write_sgi1r’ defined but not used drivers/irqchip/irq-gic-v3.c: warning: ‘gic_peek_irq’ defined but not used Signed-off-by: Geoff Levand --- Hi Marc, I'm not sure if this has gone upstream yet, but I get these warnings with Catalin's current arm64/for-next/core branch. Feel free to just fold this into your gic-v3 patch if you'll be sending out a new version. -Geoff drivers/irqchip/irq-gic-v3.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 57eaa5a..e9ee18a 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -129,11 +129,6 @@ static void gic_write_grpen1(u64 val) isb(); } -static void gic_write_sgi1r(u64 val) -{ - asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); -} - static void gic_enable_sre(void) { u64 val; @@ -200,19 +195,6 @@ static void gic_poke_irq(struct irq_data *d, u32 offset) rwp_wait(); } -static int gic_peek_irq(struct irq_data *d, u32 offset) -{ - u32 mask = 1 << (gic_irq(d) % 32); - void __iomem *base; - - if (gic_irq_in_rdist(d)) - base = gic_data_rdist_sgi_base(); - else - base = gic_data.dist_base; - - return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); -} - static void gic_mask_irq(struct irq_data *d) { gic_poke_irq(d, GICD_ICENABLER); @@ -401,6 +383,24 @@ static void gic_cpu_init(void) } #ifdef CONFIG_SMP +static void gic_write_sgi1r(u64 val) +{ + asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); +} + +static int gic_peek_irq(struct irq_data *d, u32 offset) +{ + u32 mask = 1 << (gic_irq(d) % 32); + void __iomem *base; + + if (gic_irq_in_rdist(d)) + base = gic_data_rdist_sgi_base(); + else + base = gic_data.dist_base; + + return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); +} + static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, void *hcpu) {