From patchwork Wed Jul 30 03:21:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonny Rao X-Patchwork-Id: 4645471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3765FC0338 for ; Wed, 30 Jul 2014 03:24:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 60A572012B for ; Wed, 30 Jul 2014 03:24:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6AF6920145 for ; Wed, 30 Jul 2014 03:24:44 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XCKSQ-0003Ig-IP; Wed, 30 Jul 2014 03:21:38 +0000 Received: from mail-qa0-f74.google.com ([209.85.216.74]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XCKSN-0003IE-6o for linux-arm-kernel@lists.infradead.org; Wed, 30 Jul 2014 03:21:35 +0000 Received: by mail-qa0-f74.google.com with SMTP id j15so87094qaq.3 for ; Tue, 29 Jul 2014 20:21:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=QA9Vj7jhSF726V3Bwv5YwtOEs+qyGeho+utwP3NH/VI=; b=JngvKUJt7OVe2oeVNtF5MfDbaxYYAy3FA3PBaxDdG9WzO67YMbaKoh8rP5Qc6oA+y4 NWlA4VlD0cAk1Zbdi2cPwEQyC6kEdcDxr8ztLL5M5aJHeKQ4frVu4I5jlz2/xYFuQL1U hcPHyMvYXw6GuOhxjfL2Dr/GR7WpTRWAG5Z9xsgEg1CDN/Nx2p6B4W05x5Nq/TCQS0pb +g222OdohtImLnGQSo6pWUaHUD2hwuqzOPnadkaVxclgabbiXDIzVwlJecq7JmvhCQOK JLagn41PhdnAut6HPr8Zd1T4cHwcjNmgR8P7fAbw+imbwb8SMyAnFN9qREl0SSs3dmAI w4gg== X-Gm-Message-State: ALoCoQlkSUbOsPmk0yxUyYOsBK+MVFzIq5+r4t12eoT5yTeiUC0ddthCraIJ5oySbwHBrIAKJA/1 X-Received: by 10.236.87.210 with SMTP id y58mr527759yhe.38.1406690472169; Tue, 29 Jul 2014 20:21:12 -0700 (PDT) Received: from corp2gmr1-2.hot.corp.google.com (corp2gmr1-2.hot.corp.google.com [172.24.189.93]) by gmr-mx.google.com with ESMTPS id z50si56439yhb.3.2014.07.29.20.21.12 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Jul 2014 20:21:12 -0700 (PDT) Received: from sonnyrao.mtv.corp.google.com (sonnyrao.mtv.corp.google.com [172.22.162.1]) by corp2gmr1-2.hot.corp.google.com (Postfix) with ESMTP id 0B6425A434E; Tue, 29 Jul 2014 20:21:12 -0700 (PDT) Received: by sonnyrao.mtv.corp.google.com (Postfix, from userid 129445) id ABC37A1AE5; Tue, 29 Jul 2014 20:21:11 -0700 (PDT) From: Sonny Rao To: Heiko Stuebner Subject: [PATCH] pinctrl: rockchip: fix rk3288 gpio0 pull up configuration Date: Tue, 29 Jul 2014 20:21:05 -0700 Message-Id: <1406690465-11081-1-git-send-email-sonnyrao@chromium.org> X-Mailer: git-send-email 2.0.0.526.g5318336 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140729_202135_322561_7871CF7C X-CRM114-Status: GOOD ( 12.94 ) X-Spam-Score: -1.4 (-) Cc: Sonny Rao , Linus Walleij , eddie.cai@rock-chips.com, dianders@chromium.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On rk3288, for gpio bank 0, the registers which configure pull-ups don't implement the enable bits in the upper half of the register, unlike the other gpio configuration registers, and so the kernel must perform a read-modify-write of the register to update a particular gpio's pull up settings in that bank. The current code is actually clobbering the contents of the register, so this fixes it by using regmap_update_bits and masking out only the bits which require updating. In the case of gpio0 on rk3288 the upper enable bits will just get ignored, and the other configurations won't get clobbered. Signed-off-by: Sonny Rao --- drivers/pinctrl/pinctrl-rockchip.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 5e8b2e0..bd00ae9 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -722,7 +722,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, int reg, ret; unsigned long flags; u8 bit; - u32 data; + u32 data, mask; dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); @@ -751,6 +751,14 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, /* enable the write to the equivalent lower bits */ data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); + /* + * on rk3288, gpio bank 0 doesn't support the write enable, and + * upper 16 bit are always zero, so we create a mask which will + * only update the bits we want in the lower 16, while still + * preserving write enable bits in upper 16. + */ + mask = data | (data >> 16); + switch (pull) { case PIN_CONFIG_BIAS_DISABLE: break; @@ -770,7 +778,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, return -EINVAL; } - ret = regmap_write(regmap, reg, data); + ret = regmap_update_bits(regmap, reg, mask, data); spin_unlock_irqrestore(&bank->slock, flags); break;