From patchwork Wed Aug 6 13:00:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ronald Wahl X-Patchwork-Id: 4686071 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A7E48C0338 for ; Wed, 6 Aug 2014 13:03:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 115BE200F3 for ; Wed, 6 Aug 2014 13:03:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A6B2200ED for ; Wed, 6 Aug 2014 13:03:19 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XF0qR-0004Cx-I2; Wed, 06 Aug 2014 13:01:31 +0000 Received: from iron300.routit.net ([89.146.30.10]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XF0qN-00041A-Vw for linux-arm-kernel@lists.infradead.org; Wed, 06 Aug 2014 13:01:29 +0000 X-SenderBaseSpam: None Received: from rt171bb44-46-77.routit.net (HELO raritan.com) ([46.44.171.77]) by iron300.routit.net with ESMTP; 06 Aug 2014 15:00:43 +0200 Received: from gandalf.peppercon.de ([192.168.2.24]) by raritan.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 6 Aug 2014 15:00:41 +0200 From: Ronald Wahl To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] spi: atmel: fix corruption caused by too early transfer completion Date: Wed, 6 Aug 2014 15:00:35 +0200 Message-Id: <1407330035-2212-1-git-send-email-ronald.wahl@raritan.com> X-Mailer: git-send-email 1.9.3 X-OriginalArrivalTime: 06 Aug 2014 13:00:41.0257 (UTC) FILETIME=[6D271990:01CFB176] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140806_060128_346511_05E488E9 X-CRM114-Status: GOOD ( 12.41 ) X-Spam-Score: 0.3 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PDC (peripheral DMA controller) on AT91 supports two transfer counters and associated registers - one for current and one for the next transfer. If the current transfer is done the next transfer is moved into the current transfer. Now there are two interrupts: one is raised whenever a single transfer is done (ENDRX) and the other one is raised when the current and the next transfer has finished (RXBUFF). The issue is that the driver only enables the ENDRX interrupt which may lead to queuing a new request while there is still a transfer running. This can lead to overruns and/or corruption. By using the RXBUFF interrupt only we queue new requests only when the hardware queue is empty avoiding this problem. Signed-off-by: Ronald Wahl --- drivers/spi/spi-atmel.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 113c83f..3f7d138 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -775,17 +775,17 @@ static void atmel_spi_pdc_next_xfer(struct spi_master *master, (unsigned long long)xfer->rx_dma); } - /* REVISIT: We're waiting for ENDRX before we start the next + /* REVISIT: We're waiting for RXBUFF before we start the next * transfer because we need to handle some difficult timing - * issues otherwise. If we wait for ENDTX in one transfer and - * then starts waiting for ENDRX in the next, it's difficult - * to tell the difference between the ENDRX interrupt we're - * actually waiting for and the ENDRX interrupt of the + * issues otherwise. If we wait for TXBUFE in one transfer and + * then starts waiting for RXBUFF in the next, it's difficult + * to tell the difference between the RXBUFF interrupt we're + * actually waiting for and the RXBUFF interrupt of the * previous transfer. * * It should be doable, though. Just not now... */ - spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES)); + spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES)); spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); } @@ -956,8 +956,7 @@ atmel_spi_pdc_interrupt(int irq, void *dev_id) ret = IRQ_HANDLED; - spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) - | SPI_BIT(OVRES))); + spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(OVRES))); /* Clear any overrun happening while cleaning up */ spi_readl(as, SR); @@ -966,7 +965,7 @@ atmel_spi_pdc_interrupt(int irq, void *dev_id) complete(&as->xfer_completion); - } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { + } else if (pending & (SPI_BIT(RXBUFF))) { ret = IRQ_HANDLED; spi_writel(as, IDR, pending);