From patchwork Fri Aug 8 10:19:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 4695201 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 22540C0338 for ; Fri, 8 Aug 2014 10:22:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1F3A1201C0 for ; Fri, 8 Aug 2014 10:22:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 70BDB2010F for ; Fri, 8 Aug 2014 10:22:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XFhHX-00024d-Pw; Fri, 08 Aug 2014 10:20:19 +0000 Received: from mail-we0-f176.google.com ([74.125.82.176]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XFhHP-0000sc-Ny for linux-arm-kernel@lists.infradead.org; Fri, 08 Aug 2014 10:20:13 +0000 Received: by mail-we0-f176.google.com with SMTP id q58so5361458wes.35 for ; Fri, 08 Aug 2014 03:19:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vB7RpiLgrWsXj6bjIbGYp4iaqtwYsGLefKqMqnSxUeg=; b=YNrN9YzGxO7md8Hdrase1z8HKhIN0V6hd4FbSPZ0WEsFC9GMUfPMOq6QLnxBIX9eEy 1fzcKGV8RqOWJnFmjKmE96GqhYgJkRBSJ55Pd2ytpb33M1b+4cazM+IpbvA5Da6BSNO/ Yn2H7L/+rAreLPKd8UShC9A4s41ks42dhxxBZUXJnc8lidTcsSLq2rhYhUqW1MyOj2LZ WM21tRzYcUGSwgbE9cp98KmN/zmb8VQtCoPxDnkdCbTqSo/vba9hlGyw1bQLGQ6X3RbN 0XtO4rV68xrA3FeH97fpSXsEmZdx0r50Dw6NKuAsSRMdJhTKRsJCiwxpumCHosE38kwb 1CKg== X-Gm-Message-State: ALoCoQlVeBM/Zez4GdK4FdMJsSRKOIqYsRHP0wVFq0K0Pn6OwCc1S4yHc9rNC+AN4wqQXneR3+Jk X-Received: by 10.180.39.33 with SMTP id m1mr3165558wik.82.1407493189278; Fri, 08 Aug 2014 03:19:49 -0700 (PDT) Received: from localhost.localdomain (cpc14-aztw22-2-0-cust189.18-1.cable.virginm.net. [82.45.1.190]) by mx.google.com with ESMTPSA id v14sm16309647wjw.38.2014.08.08.03.19.47 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Aug 2014 03:19:48 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kishon@ti.com, srinivas.kandagatla@gmail.com, maxime.coquelin@st.com, patrice.chotard@st.com Subject: [PATCH 1/3] phy: phy-stih41x-usb: Add usb phy support for STiH41x SoCs. Date: Fri, 8 Aug 2014 11:19:33 +0100 Message-Id: <1407493175-2611-2-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407493175-2611-1-git-send-email-peter.griffin@linaro.org> References: <1407493175-2611-1-git-send-email-peter.griffin@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140808_032012_101765_E287CBD9 X-CRM114-Status: GOOD ( 18.06 ) X-Spam-Score: -0.7 (/) Cc: peter.griffin@linaro.org, devicetree@vger.kernel.org, Peter Griffin , lee.jones@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This driver adds support for USB (1.1 and 2.0) phy for STiH415 and STiH416 System-On-Chips from STMicroelectronics. Signed-off-by: Maxime Coquelin Signed-off-by: Peter Griffin --- drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-stih41x-usb.c | 187 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 196 insertions(+) create mode 100644 drivers/phy/phy-stih41x-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 64b98d2..a4e8dec 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -180,4 +180,12 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_STIH41X_USB + tristate "STMicroelectronics USB2 PHY driver for STiH41x series" + depends on ARCH_STI + depends on GENERIC_PHY + help + Enable this to support the USB transceiver that is part of + STMicroelectronics STiH41x SoC series. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index b4f1d57..69d1702 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o +obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o diff --git a/drivers/phy/phy-stih41x-usb.c b/drivers/phy/phy-stih41x-usb.c new file mode 100644 index 0000000..8060ebb6 --- /dev/null +++ b/drivers/phy/phy-stih41x-usb.c @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2014 STMicroelectronics + * + * STMicroelectronics PHY driver for STiH41x USB. + * + * Author: Maxime Coquelin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCFG332 0x80 +#define SYSCFG2520 0x820 + +/** + * struct stih41x_usb_cfg - SoC specific PHY register mapping + * @syscfg: Offset in syscfg registers bank + * @cfg_mask: Bits mask for PHY configuration + * @cfg: Static configuration value for PHY + * @oscok: Notify the PHY oscillator clock is ready + * Setting this bit enable the PHY + */ +struct stih41x_usb_cfg { + u32 syscfg; + u32 cfg_mask; + u32 cfg; + u32 oscok; +}; + +/** + * struct stih41x_usb_phy - Private data for the PHY + * @dev: device for this controller + * @regmap: Syscfg registers bank in which PHY is configured + * @cfg: SoC specific PHY register mapping + * @clk: Oscillator used by the PHY + */ +struct stih41x_usb_phy { + struct device *dev; + struct regmap *regmap; + const struct stih41x_usb_cfg *cfg; + struct clk *clk; +}; + +static struct stih41x_usb_cfg stih415_usb_phy_cfg = { + .syscfg = SYSCFG332, + .cfg_mask = 0x3f, + .cfg = 0x38, + .oscok = BIT(6), +}; + +static struct stih41x_usb_cfg stih416_usb_phy_cfg = { + .syscfg = SYSCFG2520, + .cfg_mask = 0x33f, + .cfg = 0x238, + .oscok = BIT(6), +}; + +static int stih41x_usb_phy_init(struct phy *phy) +{ + struct stih41x_usb_phy *phy_dev = phy_get_drvdata(phy); + + return regmap_update_bits(phy_dev->regmap, phy_dev->cfg->syscfg, + phy_dev->cfg->cfg_mask, phy_dev->cfg->cfg); +} + +static int stih41x_usb_phy_power_on(struct phy *phy) +{ + struct stih41x_usb_phy *phy_dev = phy_get_drvdata(phy); + int ret; + + ret = clk_prepare_enable(phy_dev->clk); + if (ret) { + dev_err(phy_dev->dev, "Failed to enable osc_phy clock\n"); + return ret; + } + + return regmap_update_bits(phy_dev->regmap, phy_dev->cfg->syscfg, + phy_dev->cfg->oscok, phy_dev->cfg->oscok); +} + +static int stih41x_usb_phy_power_off(struct phy *phy) +{ + struct stih41x_usb_phy *phy_dev = phy_get_drvdata(phy); + int ret; + + ret = regmap_update_bits(phy_dev->regmap, phy_dev->cfg->syscfg, + phy_dev->cfg->oscok, 0); + if (ret) { + dev_err(phy_dev->dev, "Failed to clear oscok bit\n"); + return ret; + } + + clk_disable_unprepare(phy_dev->clk); + + return 0; +} + +static struct phy_ops stih41x_usb_phy_ops = { + .init = stih41x_usb_phy_init, + .power_on = stih41x_usb_phy_power_on, + .power_off = stih41x_usb_phy_power_off, + .owner = THIS_MODULE, +}; + +static const struct of_device_id stih41x_usb_phy_of_match[]; + +static int stih41x_usb_phy_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + struct stih41x_usb_phy *phy_dev; + struct device *dev = &pdev->dev; + struct phy_provider *phy_provider; + struct phy *phy; + + phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL); + if (!phy_dev) + return -ENOMEM; + + match = of_match_device(stih41x_usb_phy_of_match, &pdev->dev); + if (!match) + return -ENODEV; + + phy_dev->cfg = match->data; + + phy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + if (IS_ERR(phy_dev->regmap)) { + dev_err(dev, "No syscfg phandle specified\n"); + return PTR_ERR(phy_dev->regmap); + } + + phy_dev->clk = devm_clk_get(dev, "osc_phy"); + if (IS_ERR(phy_dev->clk)) { + dev_err(dev, "osc_phy clk not found\n"); + return PTR_ERR(phy_dev->clk); + } + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + phy = devm_phy_create(dev, &stih41x_usb_phy_ops, NULL); + if (IS_ERR(phy)) { + dev_err(dev, "failed to create Display Port PHY\n"); + return PTR_ERR(phy); + } + + phy_dev->dev = dev; + + phy_set_drvdata(phy, phy_dev); + + return 0; +} + +static const struct of_device_id stih41x_usb_phy_of_match[] = { + { .compatible = "st,stih415-usb-phy", .data = &stih415_usb_phy_cfg }, + { .compatible = "st,stih416-usb-phy", .data = &stih416_usb_phy_cfg }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, stih41x_usb_phy_of_match); + +static struct platform_driver stih41x_usb_phy_driver = { + .probe = stih41x_usb_phy_probe, + .driver = { + .name = "stih41x-usb-phy", + .owner = THIS_MODULE, + .of_match_table = stih41x_usb_phy_of_match, + } +}; +module_platform_driver(stih41x_usb_phy_driver); + +MODULE_AUTHOR("Maxime Coquelin "); +MODULE_DESCRIPTION("STMicroelectronics USB PHY driver for STiH41x series"); +MODULE_LICENSE("GPL v2");