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[216.31.211.11]) by mx.google.com with ESMTPSA id tt1sm6454597pbc.44.2014.08.14.17.12.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Aug 2014 17:12:33 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/5] ARM: BCM63XX: add BCM63138 minimal Device Tree Date: Thu, 14 Aug 2014 17:11:25 -0700 Message-Id: <1408061487-20984-4-git-send-email-f.fainelli@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1408061487-20984-1-git-send-email-f.fainelli@gmail.com> References: <1408061487-20984-1-git-send-email-f.fainelli@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140814_171255_919465_6661E284 X-CRM114-Status: GOOD ( 12.36 ) X-Spam-Score: -0.8 (/) Cc: devicetree@vger.kernel.org, Florian Fainelli , arm@kernel.org, arnd@arndb.de, cernekee@gmail.com, jpeshkin@broadcom.com, mporter@linaro.org, jogo@openwrt.org, elder@kernel.org, olof@lixom.net, mbizon@freebox.fr X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a very minimalistic BCM63138 Device Tree include file which describes the BCM63138 SoC with only the basic set of required peripherals: - Cortex A9 CPUs - ARM GIC - ARM SCU - PL310 Level-2 cache controller - ARM TWD & Global timers - ARM TWD watchdog - legacy MIPS bus (UBUS) - BCM6345-style UARTs (disabled by default) Since the PL310 L2 cache controller does not come out of reset with correct default values, we need to override the 'cache-sets' and 'cache-size' properties to get its geometry right. Signed-off-by: Florian Fainelli Acked-by: Arnd Bergmann --- Changes in v2: - removed buses 'reg' properties since they are unused - align buses 'ranges' properties on a nicer boundary - moved mpcore peripherals one level higher in the axi bus - added uart nodes since we have a driver for it (bcm63xx_uart) arch/arm/boot/dts/bcm63138.dtsi | 134 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 arch/arm/boot/dts/bcm63138.dtsi diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi new file mode 100644 index 000000000000..b7ce4da3d742 --- /dev/null +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -0,0 +1,134 @@ +/* + * Broadcom BCM63138 DSL SoCs Device Tree + */ + +#include +#include + +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63138"; + model = "Broadcom BCM63138 DSL SoC"; + interrupt-parent = <&gic>; + + aliases { + uart0 = &serial0; + uart1 = &serial1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <1>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <500000000>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "periph"; + }; + }; + + /* ARM bus */ + axi@80000000 { + compatible = "simple-bus"; + ranges = <0 0x80000000 0x84000>; + #address-cells = <1>; + #size-cells = <1>; + + L2: cache-controller@1d000 { + compatible = "arm,pl310-cache"; + reg = <0x1d000 0x1000>; + cache-unified; + cache-level = <2>; + cache-sets = <16>; + cache-size = <0x80000>; + interrupts = ; + }; + + scu: scu@1e000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000 0x100>; + }; + + gic: interrupt-controller@1e100 { + compatible = "arm,cortex-a9-gic"; + reg = <0x1f000 0x1000 + 0x1e100 0x100>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + }; + + global_timer: timer@1e200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x1e200 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + local_timer: local-timer@1e600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e600 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + twd_watchdog: watchdog@1e620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e620 0x20>; + interupts = ; + }; + }; + + /* Legacy UBUS base */ + ubus@fffe8000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8100>; + + serial0: uart@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x1b>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "periph"; + status = "disabled"; + }; + + serial1: uart@620 { + compatible = "brcm,bcm6345-uart"; + reg = <0x620 0x1b>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "periph"; + status = "disabled"; + }; + }; +};