From patchwork Fri Aug 15 09:49:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "bhupesh.sharma@freescale.com" X-Patchwork-Id: 4726741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B1029C0338 for ; Fri, 15 Aug 2014 09:53:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A5A5E201FE for ; Fri, 15 Aug 2014 09:53:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D3A9201FB for ; Fri, 15 Aug 2014 09:53:53 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XIEA3-0006bb-Tl; Fri, 15 Aug 2014 09:51:03 +0000 Received: from mail-by2lp0242.outbound.protection.outlook.com ([207.46.163.242] helo=na01-by2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XIE9n-0006IO-6L for linux-arm-kernel@lists.infradead.org; Fri, 15 Aug 2014 09:50:48 +0000 Received: from BN3PR0301CA0050.namprd03.prod.outlook.com (25.160.152.146) by BLUPR03MB309.namprd03.prod.outlook.com (10.141.48.22) with Microsoft SMTP Server (TLS) id 15.0.1010.13; Fri, 15 Aug 2014 09:50:23 +0000 Received: from BN1AFFO11FD013.protection.gbl (2a01:111:f400:7c10::100) by BN3PR0301CA0050.outlook.office365.com (2a01:111:e400:401e::18) with Microsoft SMTP Server (TLS) id 15.0.1010.18 via Frontend Transport; Fri, 15 Aug 2014 09:50:23 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD013.mail.protection.outlook.com (10.58.52.73) with Microsoft SMTP Server (TLS) id 15.0.1010.11 via Frontend Transport; Fri, 15 Aug 2014 09:50:23 +0000 Received: from b45370.ap.freescale.net ([10.214.249.36]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s7F9nIOD000811; Fri, 15 Aug 2014 02:50:17 -0700 From: Bhupesh Sharma To: , Subject: [PATCH 4/6] arm64: Add DTS support for FSL's LS2085A SoC Date: Fri, 15 Aug 2014 15:19:13 +0530 Message-ID: <1408096156-29772-5-git-send-email-bhupesh.sharma@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1408096156-29772-1-git-send-email-bhupesh.sharma@freescale.com> References: <1408096156-29772-1-git-send-email-bhupesh.sharma@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199003)(81342001)(50226001)(76482001)(50466002)(79102001)(77982001)(4396001)(64706001)(36756003)(80022001)(20776003)(77156001)(47776003)(105606002)(21056001)(50986999)(87936001)(92726001)(48376002)(76176999)(92566001)(85306004)(93916002)(85852003)(74662001)(88136002)(95666004)(89996001)(86362001)(74502001)(575784001)(104016003)(33646002)(31966008)(84676001)(83072002)(87286001)(106466001)(97736001)(26826002)(104166001)(62966002)(229853001)(46102001)(102836001)(107046002)(69596002)(81156004)(68736004)(6806004)(44976005)(19580405001)(83322001)(99396002)(81542001)(19580395003); DIR:OUT; SFP:; SCL:1; SRVR:BLUPR03MB309; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 0304E36CA3 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=bhupesh.sharma@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140815_025047_325563_3C12D129 X-CRM114-Status: GOOD ( 10.82 ) X-Spam-Score: -1.4 (-) Cc: arnd@arndb.de, Bhupesh Sharma , Will.Deacon@arm.com, stuart.yoder@freescale.com, grant.likely@secretlab.ca, arnab.basu@freescale.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the device tree support for FSL LS2085A SoC based on ARMv8 architecture. Following levels of DTSI/DTS files have been created for the LS2085A SoC family: - fsl-ls2085a.dtsi: DTS-Include file for FSL LS2085A SoC. - fsl-ls2085a-simu.dts: DTS file for FSL LS2085a software simulator model. Signed-off-by: Bhupesh Sharma Signed-off-by: Arnab Basu Signed-off-by: Stuart Yoder --- arch/arm64/boot/dts/fsl-ls2085a-simu.dts | 29 ++++++ arch/arm64/boot/dts/fsl-ls2085a.dtsi | 145 ++++++++++++++++++++++++++++++ 2 files changed, 174 insertions(+) create mode 100644 arch/arm64/boot/dts/fsl-ls2085a-simu.dts create mode 100644 arch/arm64/boot/dts/fsl-ls2085a.dtsi diff --git a/arch/arm64/boot/dts/fsl-ls2085a-simu.dts b/arch/arm64/boot/dts/fsl-ls2085a-simu.dts new file mode 100644 index 0000000..8a55710 --- /dev/null +++ b/arch/arm64/boot/dts/fsl-ls2085a-simu.dts @@ -0,0 +1,29 @@ +/* + * Device Tree file for Freescale LS2085a software Simulator model + * + * Copyright (C) 2014, Freescale Semiconductor + * + * Bhupesh Sharma + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +/include/ "fsl-ls2085a.dtsi" + +/ { + model = "Freescale Layerscape 2085a software Simulator model"; + compatible = "fsl,ls2085a-simu", "fsl,ls2085a"; + + ethernet@2210000 { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "smsc,lan91c111"; + reg = <0x0 0x2210000 0x0 0x100>; + interrupts = <0 58 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/fsl-ls2085a.dtsi b/arch/arm64/boot/dts/fsl-ls2085a.dtsi new file mode 100644 index 0000000..aca48ac --- /dev/null +++ b/arch/arm64/boot/dts/fsl-ls2085a.dtsi @@ -0,0 +1,145 @@ +/* + * Device Tree Include file for Freescale Layerscape-2085A family SoC. + * + * Copyright (C) 2014, Freescale Semiconductor + * + * Bhupesh Sharma + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* Preventing Linux from using the following memory chunk */ +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible = "fsl,ls2085a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* We have 4 clusters having 2 Cortex-A57 cores each */ + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x200>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x201>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x300>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + + cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x301>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + interrupts = <1 9 0xf04>; + + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x01>, /* Physical Secure PPI, edge triggered */ + <1 14 0x01>, /* Physical Non-Secure PPI, edge triggered */ + <1 0 0x01>, /* Virtual PPI, edge triggered */ + <1 10 0x01>; /* Hypervisor PPI, edge triggered */ + }; + + serial0: serial@21c4500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c4500 0x0 0x100>; + clock-frequency = <0>; + interrupts = <0 32 0x1>; /* edge triggered */ + }; + + serial1: serial@21c4600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c4600 0x0 0x100>; + clock-frequency = <0>; + interrupts = <0 32 0x1>; /* edge triggered */ + }; + + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x00000008 0x0c000000 0 0x40 /* MC portal base */ + 0x00000000 0x08340000 0 0x40000 >; /* MC control reg */ + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space 1 - 2 GB DRAM */ + }; +};