From patchwork Tue Aug 19 16:45:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 4744661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 67C44C0338 for ; Tue, 19 Aug 2014 16:53:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 47F9F2015A for ; Tue, 19 Aug 2014 16:53:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5547120103 for ; Tue, 19 Aug 2014 16:53:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XJmcz-0001Lw-G4; Tue, 19 Aug 2014 16:51:21 +0000 Received: from mail-wi0-f169.google.com ([209.85.212.169]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XJmcj-0000u4-HY for linux-arm-kernel@lists.infradead.org; Tue, 19 Aug 2014 16:51:06 +0000 Received: by mail-wi0-f169.google.com with SMTP id n3so5479697wiv.2 for ; Tue, 19 Aug 2014 09:50:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nzk2D8NwDPR8us2X6gDWosD4X78vVgNIn9azhM6mFHk=; b=KTsIuBpOtEMr2X9O0OV3euokslfTjaG8LJyU9bZnleKlcAhqsbEuEUrcJeAShIZAHr FXI6mSHX7LSAo1ltddtD/S3d9eLAacikJKQxn9CliqGI4prsZC740drS4RD+w+Zx2nvy Jgd9P7hIr1joGoTLSbLKdpDI7sF4OkCjgoBmTIDQAkPnkuqsCXHqaB+Nyd305q0qk0le rBTRzdpKNyp2RI0K6Fa+rFrg+pmQ6jq2mLoKeIJctcGoLllTV5z4DISsUx4cIyL2qNOo jMhtPagp6Hnit8ljLwFRTL5HGQ8wf1+/9nKGXW4UYQdK0c+IMrFlrwy8SrZcjO2ChtlW qvvw== X-Gm-Message-State: ALoCoQmbABYzIkJDt6u9Tb5EF46ZleRMu6RUjBG4lULFLCH4CFc52iFZSczelwHVlmfQk/IDTu9l X-Received: by 10.194.75.138 with SMTP id c10mr46499408wjw.9.1408467043507; Tue, 19 Aug 2014 09:50:43 -0700 (PDT) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id gc8sm36225wic.3.2014.08.19.09.50.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Aug 2014 09:50:42 -0700 (PDT) From: Daniel Thompson To: Russell King Subject: [PATCH v10 07/19] irqchip: gic: Add support for FIQ management Date: Tue, 19 Aug 2014 17:45:57 +0100 Message-Id: <1408466769-20004-8-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1408466769-20004-1-git-send-email-daniel.thompson@linaro.org> References: <1408369264-14242-1-git-send-email-daniel.thompson@linaro.org> <1408466769-20004-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140819_095105_734754_C9276E0E X-CRM114-Status: GOOD ( 18.39 ) X-Spam-Score: -0.7 (/) Cc: Nicolas Pitre , Catalin Marinas , Linus Walleij , Sricharan R , Fabio Estevam , Daniel Thompson , Nicolas Pitre , Anton Vorontsov , Ben Dooks , kgdb-bugreport@lists.sourceforge.net, kernel-team@android.com, Dave Martin , linaro-kernel@lists.linaro.org, Jason Cooper , patches@linaro.org, John Stultz , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Colin Cross , Frederic Weisbecker , Christoffer Dall X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch introduces callbacks to route interrupts to or away from the FIQ signal and registers these callbacks with the FIQ infrastructure (if the device can supports it). Both these aspects combine and allow a driver to deploy a FIQ handler without any machine specific knowledge; it can be used effectively on multi-platform kernels. Signed-off-by: Daniel Thompson Cc: Thomas Gleixner Cc: Jason Cooper Cc: Nicolas Pitre Cc: Christoffer Dall Cc: Sricharan R --- drivers/irqchip/irq-gic.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 423707c..6fa0542 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -342,6 +342,69 @@ static struct irq_chip gic_chip = { }; #ifdef CONFIG_FIQ +/* + * Shift an interrupt between Group 0 and Group 1. + * + * In addition to changing the group we also modify the priority to + * match what "ARM strongly recommends" for a system where no Group 1 + * interrupt must ever preempt a Group 0 interrupt. + */ +static void gic_set_group_irq(struct irq_data *d, int group) +{ + unsigned int grp_reg = gic_irq(d) / 32 * 4; + u32 grp_mask = 1 << (gic_irq(d) % 32); + u32 grp_val; + + unsigned int pri_reg = (gic_irq(d) / 4) * 4; + u32 pri_mask = 1 << (7 + ((gic_irq(d) % 4) * 8)); + u32 pri_val; + + raw_spin_lock(&irq_controller_lock); + + grp_val = readl_relaxed(gic_dist_base(d) + GIC_DIST_IGROUP + grp_reg); + pri_val = readl_relaxed(gic_dist_base(d) + GIC_DIST_PRI + pri_reg); + + if (group) { + grp_val |= grp_mask; + pri_val |= pri_mask; + } else { + grp_val &= ~grp_mask; + pri_val &= ~pri_mask; + } + + writel_relaxed(grp_val, gic_dist_base(d) + GIC_DIST_IGROUP + grp_reg); + writel_relaxed(pri_val, gic_dist_base(d) + GIC_DIST_PRI + pri_reg); + + raw_spin_unlock(&irq_controller_lock); +} + +static void gic_enable_fiq(struct irq_data *d) +{ + gic_set_group_irq(d, 0); +} + +static void gic_disable_fiq(struct irq_data *d) +{ + gic_set_group_irq(d, 1); +} + +static int gic_ack_fiq(struct irq_data *d) +{ + struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); + u32 irqstat, irqnr; + + irqstat = readl_relaxed(gic_data_cpu_base(gic) + GIC_CPU_INTACK); + irqnr = irqstat & GICC_IAR_INT_ID_MASK; + return irq_find_mapping(gic->domain, irqnr); +} + +static struct fiq_chip gic_fiq = { + .fiq_enable = gic_enable_fiq, + .fiq_disable = gic_disable_fiq, + .fiq_ack = gic_ack_fiq, + .fiq_eoi = gic_eoi_irq, +}; + static void __init gic_init_fiq(struct gic_chip_data *gic, irq_hw_number_t first_irq, unsigned int num_irqs) @@ -370,6 +433,12 @@ static void __init gic_init_fiq(struct gic_chip_data *gic, if (!gic->fiq_enable) return; + + /* + * FIQ is supported on this device! Register our chip data. + */ + for (i = 0; i < num_irqs; i++) + fiq_register_mapping(first_irq + i, &gic_fiq); } #else /* CONFIG_FIQ */ static inline void gic_init_fiq(struct gic_chip_data *gic,