From patchwork Tue Aug 26 05:46:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 4778261 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 72994C0338 for ; Tue, 26 Aug 2014 05:49:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 964A020145 for ; Tue, 26 Aug 2014 05:49:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9EC6020142 for ; Tue, 26 Aug 2014 05:49:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XM9bh-0001w7-By; Tue, 26 Aug 2014 05:47:49 +0000 Received: from mail-pd0-f174.google.com ([209.85.192.174]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XM9bd-0001lh-Qk for linux-arm-kernel@lists.infradead.org; Tue, 26 Aug 2014 05:47:46 +0000 Received: by mail-pd0-f174.google.com with SMTP id fp1so21737755pdb.33 for ; Mon, 25 Aug 2014 22:47:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Hq1CgYInXXj5CyI3eMGQBr2MmEj7SGNdBu7bCZDG1bM=; b=CiQmhmNnfAZQzO5rVnQGrshbYDUP5Rws5XN2yNs/r8dMvmNErF3BdxvsVt0ZJ0sowQ UWR9EoD0vcQ2P21kqrGr+zwY/EA8+Hp9Yu3NQdPgQVrpZSoZLRbZTxNvffSWcWM+f7Cq D1t+pDX7VQaBsDCI4kYkBREl0j/I1G5poz/cdm8zALx6HgVkraS94Zxj8QpxL3wpZq0G y+CgHcu5HTcaYQjGXMNenZl3YFIuGVXdbXJejXCgG4FlcrYGNRlXsCnO/8dOzHWjg/pJ 7OjhhcM6ZokRv1jpHiQttmCkxd79avTi0olyPyBdJ//IJh6YNJj/Y+hzR44Fb/bj2PzM pKtg== X-Gm-Message-State: ALoCoQnHRaK6OeV4IUd8SIGPpCipx366g/meqSbAv4VAVnSeJx7iastNdqWb7isZYs3UAWs1IIvt X-Received: by 10.66.66.101 with SMTP id e5mr35114315pat.100.1409032045302; Mon, 25 Aug 2014 22:47:25 -0700 (PDT) Received: from localhost.localdomain ([114.97.111.70]) by mx.google.com with ESMTPSA id hb1sm1696102pbd.28.2014.08.25.22.47.19 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 25 Aug 2014 22:47:24 -0700 (PDT) From: Zhangfei Gao To: Mike Turquette , haojian.zhuang@linaro.org, haifeng.yan@linaro.org, jchxue@gmail.com, xuwei5@hisilicon.com Subject: [PATCH resend 4/4] clk: hix5hd2: add I2C clocks Date: Tue, 26 Aug 2014 13:46:10 +0800 Message-Id: <1409031970-4821-5-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1409031970-4821-1-git-send-email-zhangfei.gao@linaro.org> References: <1409031970-4821-1-git-send-email-zhangfei.gao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140825_224745_893371_7FD4BCDE X-CRM114-Status: UNSURE ( 9.47 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) Cc: devicetree@vger.kernel.org, Zhangfei Gao , linux-arm-kernel@lists.infradead.org, Wei Yan X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Wei Yan hix5hd2 add I2C clocks (I2C0~i2C5) Signed-off-by: Wei Yan Signed-off-by: Zhangfei Gao --- drivers/clk/hisilicon/clk-hix5hd2.c | 25 +++++++++++++++++++++++++ include/dt-bindings/clock/hix5hd2-clock.h | 12 ++++++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c index 232c38a..5f4b5a8 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -100,6 +100,31 @@ static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = { CLK_SET_RATE_PARENT, 0x178, 0, 0, }, { HIX5HD2_WDG0_RST, "rst_wdg0", "clk_wdg0", CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, }, + /* I2C */ + {HIX5HD2_I2C0_CLK, "clk_i2c0", "100m", + CLK_SET_RATE_PARENT, 0x06c, 4, 0, }, + {HIX5HD2_I2C0_RST, "rst_i2c0", "clk_i2c0", + CLK_SET_RATE_PARENT, 0x06c, 5, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C1_CLK, "clk_i2c1", "100m", + CLK_SET_RATE_PARENT, 0x06c, 8, 0, }, + {HIX5HD2_I2C1_RST, "rst_i2c1", "clk_i2c1", + CLK_SET_RATE_PARENT, 0x06c, 9, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C2_CLK, "clk_i2c2", "100m", + CLK_SET_RATE_PARENT, 0x06c, 12, 0, }, + {HIX5HD2_I2C2_RST, "rst_i2c2", "clk_i2c2", + CLK_SET_RATE_PARENT, 0x06c, 13, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C3_CLK, "clk_i2c3", "100m", + CLK_SET_RATE_PARENT, 0x06c, 16, 0, }, + {HIX5HD2_I2C3_RST, "rst_i2c3", "clk_i2c3", + CLK_SET_RATE_PARENT, 0x06c, 17, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C4_CLK, "clk_i2c4", "100m", + CLK_SET_RATE_PARENT, 0x06c, 20, 0, }, + {HIX5HD2_I2C4_RST, "rst_i2c4", "clk_i2c4", + CLK_SET_RATE_PARENT, 0x06c, 21, CLK_GATE_SET_TO_DISABLE, }, + {HIX5HD2_I2C5_CLK, "clk_i2c5", "100m", + CLK_SET_RATE_PARENT, 0x06c, 0, 0, }, + {HIX5HD2_I2C5_RST, "rst_i2c5", "clk_i2c5", + CLK_SET_RATE_PARENT, 0x06c, 1, CLK_GATE_SET_TO_DISABLE, }, }; enum hix5hd2_clk_type { diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h index b8e3c9d..fd29c17 100644 --- a/include/dt-bindings/clock/hix5hd2-clock.h +++ b/include/dt-bindings/clock/hix5hd2-clock.h @@ -62,6 +62,18 @@ #define HIX5HD2_SD_CIU_RST 138 #define HIX5HD2_WDG0_CLK 139 #define HIX5HD2_WDG0_RST 140 +#define HIX5HD2_I2C0_CLK 141 +#define HIX5HD2_I2C0_RST 142 +#define HIX5HD2_I2C1_CLK 143 +#define HIX5HD2_I2C1_RST 144 +#define HIX5HD2_I2C2_CLK 145 +#define HIX5HD2_I2C2_RST 146 +#define HIX5HD2_I2C3_CLK 147 +#define HIX5HD2_I2C3_RST 148 +#define HIX5HD2_I2C4_CLK 149 +#define HIX5HD2_I2C4_RST 150 +#define HIX5HD2_I2C5_CLK 151 +#define HIX5HD2_I2C5_RST 152 /* complex */ #define HIX5HD2_MAC0_CLK 192