From patchwork Tue Aug 26 15:35:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 4783161 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5F28DC0338 for ; Tue, 26 Aug 2014 15:39:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 75F502011D for ; Tue, 26 Aug 2014 15:39:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49A2120117 for ; Tue, 26 Aug 2014 15:39:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XMInG-0006nt-I5; Tue, 26 Aug 2014 15:36:22 +0000 Received: from mail-by2ln0186.outbound.protection.outlook.com ([2a01:111:f400:7c0c::186] helo=na01-by2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XMImx-0006R6-T5 for linux-arm-kernel@lists.infradead.org; Tue, 26 Aug 2014 15:36:04 +0000 Received: from BN3PR0301CA0048.namprd03.prod.outlook.com (25.160.152.144) by BL2PR03MB339.namprd03.prod.outlook.com (10.141.68.23) with Microsoft SMTP Server (TLS) id 15.0.1015.9; Tue, 26 Aug 2014 15:35:40 +0000 Received: from BN1BFFO11FD020.protection.gbl (2a01:111:f400:7c10::1:142) by BN3PR0301CA0048.outlook.office365.com (2a01:111:e400:401e::16) with Microsoft SMTP Server (TLS) id 15.0.1015.19 via Frontend Transport; Tue, 26 Aug 2014 15:35:40 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD020.mail.protection.outlook.com (10.58.144.83) with Microsoft SMTP Server (TLS) id 15.0.1010.11 via Frontend Transport; Tue, 26 Aug 2014 15:35:39 +0000 Received: from dragon.ap.freescale.net ([10.192.185.230]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s7QFZUfh020382; Tue, 26 Aug 2014 08:35:36 -0700 From: Shawn Guo To: Subject: [RFC PATCH 2/2] ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver Date: Tue, 26 Aug 2014 23:35:13 +0800 Message-ID: <1409067313-32063-3-git-send-email-shawn.guo@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1409067313-32063-1-git-send-email-shawn.guo@freescale.com> References: <1409067313-32063-1-git-send-email-shawn.guo@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199003)(83072002)(44976005)(81156004)(19580395003)(50986999)(50226001)(110136001)(74502001)(92566001)(33646002)(102836001)(86362001)(81342001)(93916002)(97736001)(6806004)(50466002)(92726001)(104166001)(104016003)(83322001)(26826002)(31966008)(48376002)(76176999)(87286001)(36756003)(46102001)(106466001)(90102001)(68736004)(575784001)(77156001)(81542001)(21056001)(88136002)(80022001)(87936001)(4396001)(64706001)(105606002)(62966002)(89996001)(85306004)(69596002)(95666004)(229853001)(47776003)(20776003)(84676001)(74662001)(99396002)(77982001)(19580405001)(85852003)(107046002)(79102001)(2351001)(76482001)(217873001); DIR:OUT; SFP:; SCL:1; SRVR:BL2PR03MB339; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 03152A99FF Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140826_083604_124212_1EB5DD4E X-CRM114-Status: UNSURE ( 8.89 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) Cc: Ranjani Vaidyanathan , Shengjiu Wang , Anson Huang , kernel@pengutronix.de, Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since ENABLE and BYPASS bits of PLLs are now implemented as separate gate and mux clocks by clock drivers, the code handling these two bits can be removed from clk-pllv3 driver. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-pllv3.c | 37 ------------------------------------- 1 file changed, 37 deletions(-) diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index 61364050fccd..57de74da0acf 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -23,8 +23,6 @@ #define PLL_DENOM_OFFSET 0x20 #define BM_PLL_POWER (0x1 << 12) -#define BM_PLL_ENABLE (0x1 << 13) -#define BM_PLL_BYPASS (0x1 << 16) #define BM_PLL_LOCK (0x1 << 31) /** @@ -84,10 +82,6 @@ static int clk_pllv3_prepare(struct clk_hw *hw) if (ret) return ret; - val = readl_relaxed(pll->base); - val &= ~BM_PLL_BYPASS; - writel_relaxed(val, pll->base); - return 0; } @@ -97,7 +91,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw) u32 val; val = readl_relaxed(pll->base); - val |= BM_PLL_BYPASS; if (pll->powerup_set) val &= ~BM_PLL_POWER; else @@ -105,28 +98,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw) writel_relaxed(val, pll->base); } -static int clk_pllv3_enable(struct clk_hw *hw) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 val; - - val = readl_relaxed(pll->base); - val |= BM_PLL_ENABLE; - writel_relaxed(val, pll->base); - - return 0; -} - -static void clk_pllv3_disable(struct clk_hw *hw) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 val; - - val = readl_relaxed(pll->base); - val &= ~BM_PLL_ENABLE; - writel_relaxed(val, pll->base); -} - static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -169,8 +140,6 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, static const struct clk_ops clk_pllv3_ops = { .prepare = clk_pllv3_prepare, .unprepare = clk_pllv3_unprepare, - .enable = clk_pllv3_enable, - .disable = clk_pllv3_disable, .recalc_rate = clk_pllv3_recalc_rate, .round_rate = clk_pllv3_round_rate, .set_rate = clk_pllv3_set_rate, @@ -225,8 +194,6 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, static const struct clk_ops clk_pllv3_sys_ops = { .prepare = clk_pllv3_prepare, .unprepare = clk_pllv3_unprepare, - .enable = clk_pllv3_enable, - .disable = clk_pllv3_disable, .recalc_rate = clk_pllv3_sys_recalc_rate, .round_rate = clk_pllv3_sys_round_rate, .set_rate = clk_pllv3_sys_set_rate, @@ -299,8 +266,6 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, static const struct clk_ops clk_pllv3_av_ops = { .prepare = clk_pllv3_prepare, .unprepare = clk_pllv3_unprepare, - .enable = clk_pllv3_enable, - .disable = clk_pllv3_disable, .recalc_rate = clk_pllv3_av_recalc_rate, .round_rate = clk_pllv3_av_round_rate, .set_rate = clk_pllv3_av_set_rate, @@ -315,8 +280,6 @@ static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, static const struct clk_ops clk_pllv3_enet_ops = { .prepare = clk_pllv3_prepare, .unprepare = clk_pllv3_unprepare, - .enable = clk_pllv3_enable, - .disable = clk_pllv3_disable, .recalc_rate = clk_pllv3_enet_recalc_rate, };