From patchwork Wed Sep 3 07:36:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 4831041 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3E29C9F2EC for ; Wed, 3 Sep 2014 07:46:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 76B74201E4 for ; Wed, 3 Sep 2014 07:46:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A498A201BC for ; Wed, 3 Sep 2014 07:46:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XP5Ar-00011Z-01; Wed, 03 Sep 2014 07:40:13 +0000 Received: from dns-bn1lp0143.outbound.protection.outlook.com ([207.46.163.143] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XP5Ai-0008Iq-9h for linux-arm-kernel@lists.infradead.org; Wed, 03 Sep 2014 07:40:04 +0000 Received: from BY2PR03CA043.namprd03.prod.outlook.com (10.141.249.16) by BY2PR03MB346.namprd03.prod.outlook.com (10.141.139.15) with Microsoft SMTP Server (TLS) id 15.0.1015.9; Wed, 3 Sep 2014 07:39:41 +0000 Received: from BY2FFO11FD011.protection.gbl (2a01:111:f400:7c0c::194) by BY2PR03CA043.outlook.office365.com (2a01:111:e400:2c5d::16) with Microsoft SMTP Server (TLS) id 15.0.1019.16 via Frontend Transport; Wed, 3 Sep 2014 07:39:40 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD011.mail.protection.outlook.com (10.1.14.129) with Microsoft SMTP Server (TLS) id 15.0.1010.11 via Frontend Transport; Wed, 3 Sep 2014 07:39:40 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s837dZa3007962; Wed, 3 Sep 2014 00:39:38 -0700 From: Anson Huang To: , Subject: [PATCH 1/3] ARM: imx: add gpt_3m clk for i.mx6qdl Date: Wed, 3 Sep 2014 15:36:43 +0800 Message-ID: <1409729805-9741-2-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1409729805-9741-1-git-send-email-b20788@freescale.com> References: <1409729805-9741-1-git-send-email-b20788@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199003)(107046002)(50986999)(104166001)(33646002)(83072002)(50466002)(74502001)(31966008)(229853001)(76176999)(64706001)(83322001)(97736001)(87936001)(4396001)(19580395003)(69596002)(77982001)(81342001)(50226001)(105606002)(74662001)(47776003)(102836001)(99396002)(68736004)(36756003)(92726001)(92566001)(87286001)(6806004)(80022001)(104016003)(85306004)(81156004)(48376002)(46102001)(89996001)(76482001)(84676001)(95666004)(90102001)(21056001)(62966002)(77156001)(93916002)(79102001)(44976005)(81542001)(19580405001)(20776003)(26826002)(88136002)(106466001)(85852003)(42262002); DIR:OUT; SFP:; SCL:1; SRVR:BY2PR03MB346; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 032334F434 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Anson.Huang@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140903_004004_585747_43D1F7C5 X-CRM114-Status: UNSURE ( 8.60 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add gpt_3m clock for i.mx6qdl, as gpt can source clock from OSC, some i.MX6 series SOCs has fixed divider of 8 for gpt clock, so here add a fix clk of gpt_3m. Signed-off-by: Anson Huang --- arch/arm/mach-imx/clk-imx6q.c | 1 + include/dt-bindings/clock/imx6qdl-clock.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 2edcebf..7e6b3dd 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -194,6 +194,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); + clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); if (cpu_is_imx6dl()) { clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 323e865..9bc2e07 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -220,6 +220,7 @@ #define IMX6QDL_CLK_LVDS2_GATE 207 #define IMX6QDL_CLK_ESAI_IPG 208 #define IMX6QDL_CLK_ESAI_MEM 209 -#define IMX6QDL_CLK_END 210 +#define IMX6QDL_CLK_GPT_3M 210 +#define IMX6QDL_CLK_END 211 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */