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Wed, 3 Sep 2014 07:39:43 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s837dZa5007962; Wed, 3 Sep 2014 00:39:41 -0700 From: Anson Huang To: , Subject: [PATCH 3/3] ARM: imx: source gpt per clk from OSC for system timer Date: Wed, 3 Sep 2014 15:36:45 +0800 Message-ID: <1409729805-9741-4-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1409729805-9741-1-git-send-email-b20788@freescale.com> References: <1409729805-9741-1-git-send-email-b20788@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(199003)(189002)(99396002)(68736004)(76176999)(50226001)(81342001)(81156004)(31966008)(81542001)(69596002)(62966002)(74662001)(74502001)(79102001)(104166001)(47776003)(102836001)(106466001)(85306004)(105606002)(77156001)(84676001)(76482001)(80022001)(83072002)(85852003)(19580395003)(87936001)(64706001)(46102001)(92566001)(88136002)(36756003)(92726001)(21056001)(77982001)(48376002)(50986999)(97736001)(33646002)(20776003)(89996001)(229853001)(95666004)(93916002)(6806004)(87286001)(19580405001)(83322001)(575784001)(50466002)(104016003)(26826002)(4396001)(44976005)(90102001)(107046002)(42262002); DIR:OUT; SFP:; SCL:1; SRVR:BLUPR03MB342; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:;UriScan:; X-Forefront-PRVS: 032334F434 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Anson.Huang@freescale.com; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140903_004007_865413_F701024A X-CRM114-Status: GOOD ( 14.48 ) X-Spam-Score: -1.4 (-) Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, 3b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, 3b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: Anson Huang --- arch/arm/mach-imx/time.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index bf92e5a..54d23c7 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -60,11 +60,15 @@ #define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_COMP (1 << 0) -/* MX31, MX35, MX25, MX5 */ +/* MX31, MX35, MX25, MX5, MX6 */ #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ #define V2_TCTL_CLK_IPG (1 << 6) #define V2_TCTL_CLK_PER (2 << 6) +#define V2_TCTL_CLK_OSC_DIV8 (5 << 6) +#define V2_TCTL_CLK_OSC (7 << 6) #define V2_TCTL_FRR (1 << 9) +#define V2_TCTL_24MEN (1 << 10) +#define V2_TPRER_PRE24M 12 #define V2_IR 0x0c #define V2_TSTAT 0x08 #define V2_TSTAT_OF1 (1 << 0) @@ -293,7 +297,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) static void __init _mxc_timer_init(int irq, struct clk *clk_per, struct clk *clk_ipg) { - uint32_t tctl_val; + uint32_t tctl_val, tprer_val; if (IS_ERR(clk_per)) { pr_err("i.MX timer: unable to get clk\n"); @@ -312,10 +316,25 @@ static void __init _mxc_timer_init(int irq, __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - if (timer_is_v2()) - tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - else + if (timer_is_v2()) { + if ((cpu_is_imx6q() && imx_get_soc_revision() > + IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl() || + cpu_is_imx6sx()) { + tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR | + V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (cpu_is_imx6dl() || cpu_is_imx6sx()) { + /* 24 / 8 = 3 MHz */ + tprer_val = 7 << V2_TPRER_PRE24M; + __raw_writel(tprer_val, timer_base + MXC_TPRER); + tctl_val |= V2_TCTL_24MEN; + } + } else { + tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | + V2_TCTL_WAITEN | MXC_TCTL_TEN; + } + } else { tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; + } __raw_writel(tctl_val, timer_base + MXC_TCTL);