From patchwork Thu Sep 11 15:52:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 4889451 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9F7539F371 for ; Thu, 11 Sep 2014 15:55:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 676AD20260 for ; Thu, 11 Sep 2014 15:55:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2EC772025B for ; Thu, 11 Sep 2014 15:55:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XS6gV-0000w3-Qr; Thu, 11 Sep 2014 15:53:23 +0000 Received: from mail-pd0-x22d.google.com ([2607:f8b0:400e:c02::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XS6fk-0008AJ-BN for linux-arm-kernel@lists.infradead.org; Thu, 11 Sep 2014 15:52:37 +0000 Received: by mail-pd0-f173.google.com with SMTP id ft15so11517771pdb.18 for ; Thu, 11 Sep 2014 08:52:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=H+GObuDs5bHAw6NKOGI2z4eyqcyZzSwM+zJcphw5pCE=; b=NQWlFr1KPAsqp7e12mp7AtOMNdBbZuDti1a+N7RhoLwAHL4Jzf/6S5ty9C60iV2UfQ bnxwB8rsk4hFwPk2UG8MVATS1uOOcGAix98t2MN7/a6LnTtoqGSmG9a6xGVSpTq5P5gG ejWpMqIx/7/MH7zXT+gq8g4SndPR6x1MmnDIQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=H+GObuDs5bHAw6NKOGI2z4eyqcyZzSwM+zJcphw5pCE=; b=m1v4UN1qCZnCOEDoUhCgR++ARAew+WBx2eO8RMcjaND3fERxSW2o3wiUQW+kZEGvX+ 4Wz7LlDTOQzh88GaqY74n9xnE2HKbfCrSyEZ9ZDYhcv74iioxkThToj5ZmwKpcPPjRpK kfzl3s2D1RdGqdNfCyBXsQgIB2OBiH+jy/4rqtD7Rhe7Vim6aZva84UyRIFJsoZelAP5 rabjen+1x18ozsKrk/lRGYm6NrKgP577QoGtdz3pCb+jKIognuJXsbpJtMrP4kWMZl1P nPpxa8qHs61hPj8+OeOJl+CHrErxP6r0YbgMER2u6BWnL56h/+Vj2XETToqm6sIFulgo H3EQ== X-Gm-Message-State: ALoCoQnoGXJlk6WsqXhULJJ8lbmedV/S7PS5wRkqXQItm27krLQjYY/ZTCkT54Fa/V2Z5RT8RWVi X-Received: by 10.70.36.138 with SMTP id q10mr1460053pdj.88.1410450735098; Thu, 11 Sep 2014 08:52:15 -0700 (PDT) Received: from tictac.mtv.corp.google.com (tictac.mtv.corp.google.com [172.22.162.15]) by mx.google.com with ESMTPSA id v1sm1386137pdn.93.2014.09.11.08.52.13 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Sep 2014 08:52:14 -0700 (PDT) From: Doug Anderson To: olof@lixom.net Subject: [PATCH] clocksource: arch_timer: Allow the device tree to specify the physical timer Date: Thu, 11 Sep 2014 08:52:07 -0700 Message-Id: <1410450727-8182-1-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140911_085236_472196_00FA230E X-CRM114-Status: GOOD ( 16.24 ) X-Spam-Score: -0.8 (/) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Lorenzo Pieralisi , Daniel Lezcano , pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, Marc Zyngier , Stephen Boyd , Sudeep Holla , Will Deacon , Doug Anderson , linux-kernel@vger.kernel.org, robh+dt@kernel.org, Christopher Covington , Catalin Marinas , galak@codeaurora.org, Thomas Gleixner , Sonny Rao , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some 32-bit (ARMv7) systems are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset between the virtual and physical counters. Each core gets a different random offset. On systems like the above, it doesn't make sense to use the virtual counter. There's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. Let's add a property to the device tree to say that we shouldn't use the virtual timer. Firmware could potentially remove this property before passing the device tree to the kernel if it really wants the kernel to use a virtual timer. Note that it's been said that ARM64 (ARMv8) systems the firmware and kernel really can't be architected as described above. That means using the physical timer like this really only makes sense for ARMv7 systems. In order for this patch to do anything useful, we also need Sonny's patch at Signed-off-by: Doug Anderson Signed-off-by: Sonny Rao --- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ drivers/clocksource/arm_arch_timer.c | 3 +++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index 37b2caf..876d32b 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -22,6 +22,12 @@ to deliver its interrupts via SPIs. - always-on : a boolean property. If present, the timer is powered through an always-on power domain, therefore it never loses context. +** Optional properties: + +- arm,use-physical-timer : Don't ever use the virtual timer, just use the + physical one. Not supported for ARM64. + + Example: timer { diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 5163ec1..8ca07a9 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -649,6 +649,9 @@ static void __init arch_timer_init(struct device_node *np) arch_timer_ppi[i] = irq_of_parse_and_map(np, i); arch_timer_detect_rate(NULL, np); + if (of_property_read_bool(np, "arm,use-physical-timer")) + arch_timer_use_virtual = false; + /* * If HYP mode is available, we know that the physical timer * has been configured to be accessible from PL1. Use it, so