From patchwork Thu Sep 11 17:00:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 4889721 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AB38D9F32F for ; Thu, 11 Sep 2014 17:02:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 68E212025A for ; Thu, 11 Sep 2014 17:02:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 12FFE20260 for ; Thu, 11 Sep 2014 17:02:44 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XS7jW-0003Yg-JT; Thu, 11 Sep 2014 17:00:34 +0000 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XS7jU-0003SX-FR for linux-arm-kernel@lists.infradead.org; Thu, 11 Sep 2014 17:00:33 +0000 Received: by mail-pa0-f47.google.com with SMTP id ey11so11904392pad.6 for ; Thu, 11 Sep 2014 10:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=c3kjDCLSAqaJqIDoc3g7y1aPm7NiftP0wesROV5Kp24=; b=GdvJ/sIr4fsj83N0RNLpo7l0K/G4bp5rGQ6szJXcWAK9PX97X0jFqRStw+r9giGcrz TZodITrN3qc4LojNkRAiILuxZMsZR3ABfgbh64dDM6kV8bczkQp95AOU7UZIByU1iIPJ ZXTg8MytmVQDQr7h66yYrJ7BtTxEYk/bDTxn0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=c3kjDCLSAqaJqIDoc3g7y1aPm7NiftP0wesROV5Kp24=; b=mLxqdkZDGc5xfJU1Q9tg2rg/NPt8xEWZf7ocP4AR/RFW0D8Cr6h5/y5e18FGFwO+f+ 01ifAzwPLYOalpqsO/SRu8qCeiDxKJJN0KP+vw4TYE7rP0Tpo1qd8qbMjx7Azs9K3h5o PPHf2nfbBTEmhbD0uNqOKsPttKFfsCJLtq/SKq9FYMXfowGvcfl6RV1t7RXJtNunzIAq ZAjdOaxs1YJrhDusql9y4EG1suu0xE5f6uN75O9UW797wgAwlSRhh1tFwqZmMj/VKDKx hcCAB5huyzuVvQzHjxW7bN5QhjO9232gmcoACRpXX31j3O80DMVUxGV5jI0DlzQT/NOa UAeQ== X-Gm-Message-State: ALoCoQlrBStTbemeM5p12uDNGy7S07ykZbNJr6At54i76UU0qhHEcwprA7JHSll0ZF5VAK0EVkTy X-Received: by 10.68.191.134 with SMTP id gy6mr3600527pbc.2.1410454810637; Thu, 11 Sep 2014 10:00:10 -0700 (PDT) Received: from tictac.mtv.corp.google.com (tictac.mtv.corp.google.com [172.22.162.15]) by mx.google.com with ESMTPSA id qz2sm1653420pab.27.2014.09.11.10.00.09 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Sep 2014 10:00:09 -0700 (PDT) From: Doug Anderson To: olof@lixom.net Subject: [PATCH v3] clocksource: arch_timer: Allow the device tree to specify the physical timer Date: Thu, 11 Sep 2014 10:00:01 -0700 Message-Id: <1410454801-14231-1-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140911_100032_550188_68A704B9 X-CRM114-Status: GOOD ( 17.22 ) X-Spam-Score: -0.8 (/) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Lorenzo Pieralisi , Daniel Lezcano , pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, Marc Zyngier , Stephen Boyd , Sudeep Holla , Will Deacon , Doug Anderson , linux-kernel@vger.kernel.org, galak@codeaurora.org, robh+dt@kernel.org, Christopher Covington , Catalin Marinas , Nathan Lynch , Thomas Gleixner , Sonny Rao , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some 32-bit (ARMv7) systems are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) On systems like the above, it doesn't make sense to use the virtual counter. There's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. Let's add a property to the device tree to say that we shouldn't use the virtual timer. Firmware could potentially remove this property before passing the device tree to the kernel if it really wants the kernel to use a virtual timer. Note that it's been said that ARM64 (ARMv8) systems the firmware and kernel really can't be architected as described above. That means using the physical timer like this really only makes sense for ARMv7 systems. In order for this patch to do anything useful, we also need Sonny's patch at Signed-off-by: Doug Anderson Signed-off-by: Sonny Rao --- Changes in v3: - Wording changes to bindings and patch desc as per Will Deacon Changes in v2: - Add "#ifdef CONFIG_ARM" as per Will Deacon Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ drivers/clocksource/arm_arch_timer.c | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index 37b2caf..e28fced 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -22,6 +22,12 @@ to deliver its interrupts via SPIs. - always-on : a boolean property. If present, the timer is powered through an always-on power domain, therefore it never loses context. +** Optional properties: + +- arm,use-physical-timer : Don't ever use the virtual timer, just use the + physical one. Only supported for ARM (not ARM64). + + Example: timer { diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 5163ec1..e7aa256 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -649,6 +649,11 @@ static void __init arch_timer_init(struct device_node *np) arch_timer_ppi[i] = irq_of_parse_and_map(np, i); arch_timer_detect_rate(NULL, np); +#ifdef CONFIG_ARM + if (of_property_read_bool(np, "arm,use-physical-timer")) + arch_timer_use_virtual = false; +#endif + /* * If HYP mode is available, we know that the physical timer * has been configured to be accessible from PL1. Use it, so