From patchwork Tue Sep 16 12:52:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 4917801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4CA219F349 for ; Tue, 16 Sep 2014 12:54:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A8A90201E4 for ; Tue, 16 Sep 2014 12:56:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2B4B200FF for ; Tue, 16 Sep 2014 12:56:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XTsGQ-0004L9-L5; Tue, 16 Sep 2014 12:53:46 +0000 Received: from mailout2.w1.samsung.com ([210.118.77.12]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XTsGM-00049Y-Mi for linux-arm-kernel@lists.infradead.org; Tue, 16 Sep 2014 12:53:43 +0000 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NBZ00CL2VXL2G00@mailout2.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 16 Sep 2014 13:56:09 +0100 (BST) X-AuditID: cbfec7f4-b7f156d0000063c7-c1-541832be1912 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id BA.23.25543.EB238145; Tue, 16 Sep 2014 13:53:18 +0100 (BST) Received: from AMDC1943.digital.local ([106.116.151.171]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NBZ004V6VSPGW60@eusync2.samsung.com>; Tue, 16 Sep 2014 13:53:18 +0100 (BST) From: Krzysztof Kozlowski To: Russell King , Will Deacon , "David A. Long" , Mark Rutland , Vinayak Kale , Laura Abbott , Krzysztof Kozlowski , Nicolas Pitre , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: cacheflush: Fix exynos build breakage on ARMv6 by using macros for ISB/DSB Date: Tue, 16 Sep 2014 14:52:59 +0200 Message-id: <1410871979-12470-1-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrELMWRmVeSWpSXmKPExsVy+t/xK7r7jCRCDL62iFpsnLGe1WLqwyds Fh/3LGCzeP3C0KJ3wVU2i7NNb9gttnfOYLfY9Pgaq8XlXXPYLG5f5rVYe+Quu8XS6xeZLD49 +8dusWrXH0aLec9Os1m8/HiCxUHA4+P6T4wea+atYfRoae5h87jc18vksXPWXXaPTas62Tzu XNvD5rF5Sb1H35ZVjB6fN8kFcEVx2aSk5mSWpRbp2yVwZdw6soyl4KlIxa7Lc9kbGP8IdDFy ckgImEis6T3KDmGLSVy4t56ti5GLQ0hgKaPEj++XmSGcPiaJ1UvPMoJUsQkYS2xevgSsSkSg hVni3vmzbCAJZoEmJokp+3hBbGGBJIlzW++xgNgsAqoSr1ovgDXzCrhLvF20lwlinZzEyWOT WScwci9gZFjFKJpamlxQnJSea6hXnJhbXJqXrpecn7uJERKuX3YwLj5mdYhRgINRiYc34594 iBBrYllxZe4hRgkOZiURXg9NiRAh3pTEyqrUovz4otKc1OJDjEwcnFINjIYzVEyYNqQrN0xv St/SVKOrl/T6Ze29uVXr5vZfWPrrk33r53d2ExfHTa8OYE6L/X3u1SrpbqG8e4lTmbsUDu1i zfF/Kuo//d1xL3Yn+7ZN56fkCbfvL5GbHP/Qfs+dSV3Hl5XucrTsEl9wq8Tr2bc/rH9rPR9m 1d2/uyPKee36Pze4OLs2GCqxFGckGmoxFxUnAgA+IuvRNQIAAA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140916_055342_891729_94C2C41D X-CRM114-Status: GOOD ( 11.74 ) X-Spam-Score: -5.7 (-----) Cc: Kukjin Kim , Bartlomiej Zolnierkiewicz , Tomasz Figa , Kyungmin Park , Mark Brown , Marek Szyprowski X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This fixes build breakage of platsmp.c if ARMv6 was chosen for compile time options (e.g. by building allmodconfig): $ make allmodconfig $ make CC arch/arm/mach-exynos/platsmp.o /tmp/ccdQM0Eg.s: Assembler messages: /tmp/ccdQM0Eg.s:432: Error: selected processor does not support ARM mode `isb ' /tmp/ccdQM0Eg.s:437: Error: selected processor does not support ARM mode `isb ' /tmp/ccdQM0Eg.s:438: Error: selected processor does not support ARM mode `dsb ' make[1]: *** [arch/arm/mach-exynos/platsmp.o] Error 1 The error was introduced in commit "ARM: EXYNOS: Move code from hotplug.c to platsmp.c". Previously code using v7_exit_coherency_flush() macro was built with '-march=armv7-a' flag but this flag dissapeared during the movement. Use isb() and dsb() macros in v7_exit_coherency_flush() so the proper code will be generated for ARMv6. Signed-off-by: Krzysztof Kozlowski Reported-by: Mark Brown Link: http://www.spinics.net/lists/linux-samsung-soc/msg36790.html --- arch/arm/include/asm/cacheflush.h | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 79ecb4f34ffb..b74eeec971c0 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -464,22 +464,27 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) * CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering * trampoline are inserted by the linker and to keep sp 64-bit aligned. */ -#define v7_exit_coherency_flush(level) \ +#define v7_exit_coherency_flush(level) do { \ asm volatile( \ "stmfd sp!, {fp, ip} \n\t" \ "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \ "bic r0, r0, #"__stringify(CR_C)" \n\t" \ "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \ - "isb \n\t" \ + : : : "r0","r1","r2","r3","r4","r5","r6","r7", \ + "r9","r10","lr","memory" ); \ + isb(); \ + asm volatile( \ "bl v7_flush_dcache_"__stringify(level)" \n\t" \ "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \ "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \ "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \ - "isb \n\t" \ - "dsb \n\t" \ - "ldmfd sp!, {fp, ip}" \ : : : "r0","r1","r2","r3","r4","r5","r6","r7", \ - "r9","r10","lr","memory" ) + "r9","r10","lr","memory" ); \ + isb(); \ + dsb(); \ + asm volatile( \ + "ldmfd sp!, {fp, ip}" ); \ + } while (0) int set_memory_ro(unsigned long addr, int numpages); int set_memory_rw(unsigned long addr, int numpages);