From patchwork Wed Sep 17 19:59:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 4926421 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 06797BEEA5 for ; Wed, 17 Sep 2014 20:02:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9FCE62015D for ; Wed, 17 Sep 2014 20:02:36 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 38C7020117 for ; Wed, 17 Sep 2014 20:02:35 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XULOf-0000kZ-2z; Wed, 17 Sep 2014 20:00:13 +0000 Received: from mail-ie0-f202.google.com ([209.85.223.202]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XULON-0007sL-RK for linux-arm-kernel@lists.infradead.org; Wed, 17 Sep 2014 19:59:56 +0000 Received: by mail-ie0-f202.google.com with SMTP id rd18so412295iec.5 for ; Wed, 17 Sep 2014 12:59:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YA6ab4jqp5Kz1VwYufoxGsThVV7zmic7mEcpChH7fyc=; b=Kses24fou9+kQBC2eXPGAV/YZ2+O9a7qdLTlDgCrLJ8ynjwRxGGjAtpJalsq5LEGFJ xogcC53yHhPbg99lCx9hMDNs7BrSn6OmK66trL0N3jxXzbbsbWsNvaGBb4TY4Sws7oYV cpiAzMoyH7d1OwUzWR8248XmkjAAJx1a6FXCmapfLT60yQa/giVyGjYnCxMcA9YODpEu /CR8SjGf/2+JH9vuKfuyRLqDRkJl4YViu+lo/S9Ul6k4MntE4fX3X5k4WybhzvQ/rtf1 NRn9Cu7GOdjOgBgKWtbJX+pnLZ9nW013ONagliJCEw+5EcH6zBSRvE1kiKCkBCn5FTV2 SB1g== X-Gm-Message-State: ALoCoQlGKX9DEx0SgHvrzRsDLi+LDJbfdhE0r7xiUvUGo4I1gY9s8Bnm8/tzMc/U9fQwFRv4jwO0 X-Received: by 10.43.85.198 with SMTP id ap6mr658921icc.29.1410983976637; Wed, 17 Sep 2014 12:59:36 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id l45si874396yha.2.2014.09.17.12.59.35 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Sep 2014 12:59:36 -0700 (PDT) Received: from abrestic.mtv.corp.google.com ([172.22.65.70]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id O25U5G7U.1; Wed, 17 Sep 2014 12:59:36 -0700 Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id BF7E8220B61; Wed, 17 Sep 2014 12:59:34 -0700 (PDT) From: Andrew Bresticker To: Stephen Warren , Thierry Reding , linux-tegra@vger.kernel.org Subject: [PATCH v4 5/9] of: Add NVIDIA Tegra xHCI controller binding Date: Wed, 17 Sep 2014 12:59:26 -0700 Message-Id: <1410983970-7043-6-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1410983970-7043-1-git-send-email-abrestic@chromium.org> References: <1410983970-7043-1-git-send-email-abrestic@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140917_125955_977791_5CAF2F45 X-CRM114-Status: GOOD ( 13.93 ) X-Spam-Score: -1.6 (-) Cc: Mark Rutland , devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Russell King , Mathias Nyman , Pawel Moll , Ian Campbell , Andrew Bresticker , Greg Kroah-Hartman , Linus Walleij , Jassi Brar , linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , Rob Herring , Alan Stern , linux-arm-kernel@lists.infradead.org, Kumar Gala , Grant Likely , Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device-tree binding documentation for the xHCI controller present on Tegra124 and later SoCs. Signed-off-by: Andrew Bresticker Reviewed-by: Stephen Warren --- No changes from v3. Changes from v2: - Added mbox-names property. Changes from v1: - Updated to use common mailbox bindings. - Added remaining XUSB-related clocks and resets. - Updated list of power supplies to be more accurate wrt to the hardware. --- .../bindings/usb/nvidia,tegra124-xhci.txt | 104 +++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt new file mode 100644 index 0000000..51a7751 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt @@ -0,0 +1,104 @@ +NVIDIA Tegra xHCI controller +============================ + +The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed +by the Tegra XUSB pad controller. + +Required properties: +-------------------- + - compatible: Should be "nvidia,tegra124-xhci". + - reg: Address and length of the register sets. There should be three + entries in the following order: xHCI host registers, FPCI registers, and + IPFS registers. + - interrupts: xHCI host interrupt. + - clocks: Must contain an entry for each entry in clock-names. + See ../clock/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - xusb_host + - xusb_host_src + - xusb_dev + - xusb_dev_src + - xusb_falcon_src + - xusb_ss + - xusb_ss_src + - xusb_ss_div2 + - xusb_hs_src + - xusb_fs_src + - pll_u_480m + - clk_m + - pll_e + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - xusb_host + - xusb_dev + - xusb_ss + - xusb + Note that xusb_dev is the shared reset for xusb_dev and xusb_dev_src and + that xusb is the shared reset for xusb_{ss,hs,fs,falcon,host}_src. + - mboxes: Must contain an entry for the XUSB mailbox channel. + See ../mailbox/mailbox.txt for details. + - mbox-names: Must include the following entries: + - xusb + +Optional properties: +-------------------- + - phys: Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. + - phy-names: Should include an entry for each PHY used by the controller. + May be a subset of the following: + - utmi-{0,1,2} + - hsic-{0,1} + - usb3-{0,1} + - avddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05V. + - dvddio-pex-supply: PCIe/USB3 digital logic power supply. Must supply 1.05V. + - avdd-usb-supply: USB controller power supply. Must supply 3.3V. + - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8V. + - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05V. + - avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05V. + - hvdd-pex-supply: High-voltage PCIe/USB3 power supply. Must supply 3.3V. + - hvdd-pex-plle-supply: High-voltage PLLE power supply. Must supply 3.3V. + +Example: +-------- + usb@0,70090000 { + compatible = "nvidia,tegra124-xhci"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70098000 0x0 0x1000>, + <0x0 0x70099000 0x0 0x1000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_DEV>, + <&tegra_car TEGRA124_CLK_XUSB_DEV_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_host_src", "xusb_dev", + "xusb_dev_src", "xusb_falcon_src", "xusb_ss", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 95>, <&tegra_car 156>, + <&tegra_car 143>; + reset-names = "xusb_host", "xusb_dev", "xusb_ss", "xusb"; + mboxes = <&xusb_mbox>; + mbox-names = "xusb"; + phys = <&padctl TEGRA_XUSB_PADCTL_UTMI_P1>, /* mini-PCIe USB */ + <&padctl TEGRA_XUSB_PADCTL_UTMI_P2>, /* USB A */ + <&padctl TEGRA_XUSB_PADCTL_USB3_P0>; /* USB A */ + phy-names = "utmi-1", "utmi-2", "usb3-0"; + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-usb-supply = <&vdd_3v3_lp0>; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-supply = <&vdd_3v3_lp0>; + hvdd-pex-plle-supply = <&vdd_3v3_lp0>; + };