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Mon, 22 Sep 2014 13:47:26 +0900 (KST) From: Abhilash Kesavan To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, catalin.marinas@arm.com Subject: [PATCH v5 1/8] clk: samsung: add support for 145xx and 1460x PLLs Date: Mon, 22 Sep 2014 10:17:01 +0530 Message-id: <1411361228-18279-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1411361228-18279-1-git-send-email-a.kesavan@samsung.com> References: <1411361228-18279-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMLMWRmVeSWpSXmKPExsWyRsSkWvf+SvkQg32HmCzeL+thtJh/5Byr xZq/ShabHl9jtZhxfh+TxaJt/5ktVu36w+jA7rFm3hpGj52z7rJ7bF5S7/F5k1wASxSXTUpq TmZZapG+XQJXxpk9B9gL5stXrFjxgLWB8bVkFyMnh4SAicT1+RNZIWwxiQv31rN1MXJxCAks ZZToenqDGaZo24IuZojEdEaJ/d8Ws0M4fUwSvyc8AmtnE9CTWPDvK1iViEATo8TFE6vB2pkF giWWf/jBBmILC3hJHHq0lh3EZhFQlbjQ9oOpi5GDg1fAVeLPPV8QU0JAQWLOJBuQCk4BN4lX c76AVQgBVcy4nQYyXUJgMrvE5fP7WCGmCEh8m3yIBaJVVmLTAaibJSUOrrjBMoFReAEjwypG 0dSC5ILipPQiY73ixNzi0rx0veT83E2MwLA+/e9Z/w7GuwesDzEKcDAq8fD+aJEPEWJNLCuu zD3EaAq0YSKzlGhyPjB68kriDY3NjCxMTUyNjcwtzZTEeRdK/QwWEkhPLEnNTk0tSC2KLyrN SS0+xMjEwSnVwOh9j/GJ4ZU58rlPX6V9/mZx+8jt5hyJXbUtgXM6jCcvyDL5c99zweGN7za7 v3oYyjXVQHTNqi33t/xZfrpP8+zZXa9uMq3yPcW5+f2aWYZHr9TUSOREJO2Lzttxnz9npv9l Td5ouzMMDXdrZmrNu+Xnk3H+wtQqWY10de83yfycHEvPOjk63mtSYinOSDTUYi4qTgQAb3KZ E2YCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLIsWRmVeSWpSXmKPExsVy+t9jQd17K+VDDG7sN7F4v6yH0WL+kXOs Fmv+KllsenyN1WLG+X1MFou2/We2WLXrD6MDu8eaeWsYPXbOusvusXlJvcfnTXIBLFENjDYZ qYkpqUUKqXnJ+SmZeem2St7B8c7xpmYGhrqGlhbmSgp5ibmptkouPgG6bpk5QAcoKZQl5pQC hQISi4uV9O0wTQgNcdO1gGmM0PUNCYLrMTJAAwlrGDPO7DnAXjBfvmLFigesDYyvJbsYOTkk BEwkti3oYoawxSQu3FvP1sXIxSEkMJ1RYv+3xewQTh+TxO8Jj1hBqtgE9CQW/PvKDJIQEWhi lLh4YjVYO7NAsMTyDz/YQGxhAS+JQ4/WsoPYLAKqEhfafjB1MXJw8Aq4Svy55wtiSggoSMyZ ZANSwSngJvFqzhewCiGgihm30yYw8i5gZFjFKJpakFxQnJSea6RXnJhbXJqXrpecn7uJERw1 z6R3MK5qsDjEKMDBqMTD+6NFPkSINbGsuDL3EKMEB7OSCO/RHKAQb0piZVVqUX58UWlOavEh RlOgkyYyS4km5wMjOq8k3tDYxNzU2NTSxMLEzFJJnPdgq3WgkEB6YklqdmpqQWoRTB8TB6dU A2O6f5P5fuMpLw+umjBT52norpbDOn/q+063HFZ3uawT4/34i+WhCFsXlyk58TL7p9Xr73z8 QkjQ+maOwLy4kpdBz7SVAjo/uYgH9z6b+9v/qnvr18ecHqLPdnZE+8pJTy65q7XpQ3wS77w+ 3ZBUGf23F+R1pp+u+DvxQ7r4v00h0/0MVp93LlBiKc5INNRiLipOBABgSGRHsAIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140921_214749_833176_8D4B082E X-CRM114-Status: GOOD ( 12.75 ) X-Spam-Score: -5.8 (-----) Cc: naveenkrishna.ch@gmail.com, kesavan.abhilash@gmail.com, tomasz.figa@gmail.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Naveen Krishna Ch PLL145xx is similar to PLL35xx and PLL1460x is almost similar to PLL46xx with minor differences in bit positions. Hence, reuse the functions defined for pll_35xx and pll_46xx to support 145xx and 1460x PLLs respectively. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Cc: Tomasz Figa Cc: Mike Turquette --- drivers/clk/samsung/clk-pll.c | 25 ++++++++++++++++++++----- drivers/clk/samsung/clk-pll.h | 4 ++++ 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b07fad2..9d70e5c 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = { #define PLL46XX_VSEL_MASK (1) #define PLL46XX_MDIV_MASK (0x1FF) +#define PLL1460X_MDIV_MASK (0x3FF) + #define PLL46XX_PDIV_MASK (0x3F) #define PLL46XX_SDIV_MASK (0x7) #define PLL46XX_VSEL_SHIFT (27) @@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, pll_con0 = __raw_readl(pll->con_reg); pll_con1 = __raw_readl(pll->con_reg + 4); - mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? + PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : pll_con1 & PLL46XX_KDIV_MASK; - shift = pll->type == pll_4600 ? 16 : 10; + shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; + fvco *= (mdiv << shift) + kdiv; do_div(fvco, (pdiv << sdiv)); fvco >>= shift; @@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, lock = 0xffff; /* Set PLL PMS and VSEL values. */ - con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + if (pll->type == pll_1460x) { + con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | + (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); + } else { + con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); + con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; + } + con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | (rate->pdiv << PLL46XX_PDIV_SHIFT) | - (rate->sdiv << PLL46XX_SDIV_SHIFT) | - (rate->vsel << PLL46XX_VSEL_SHIFT); + (rate->sdiv << PLL46XX_SDIV_SHIFT); /* Set PLL K, MFR and MRR values. */ con1 = __raw_readl(pll->con_reg + 0x4); @@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, /* clk_ops for 35xx and 2550 are similar */ case pll_35xx: case pll_2550: + case pll_1450x: + case pll_1451x: + case pll_1452x: if (!pll->rate_table) init.ops = &samsung_pll35xx_clk_min_ops; else @@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_4600: case pll_4650: case pll_4650c: + case pll_1460x: if (!pll->rate_table) init.ops = &samsung_pll46xx_clk_min_ops; else diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c0ed4d4..213de9a 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -33,6 +33,10 @@ enum samsung_pll_type { pll_s3c2440_mpll, pll_2550xx, pll_2650xx, + pll_1450x, + pll_1451x, + pll_1452x, + pll_1460x, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \