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Mon, 22 Sep 2014 01:39:03 -0700 From: Jingchang Lu To: Subject: [PATCHv4 2/6] ARM: dts: Add initial LS1021A QDS board dts support Date: Mon, 22 Sep 2014 15:45:48 +0800 Message-ID: <1411371952-5618-3-git-send-email-jingchang.lu@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1411371952-5618-1-git-send-email-jingchang.lu@freescale.com> References: <1411371952-5618-1-git-send-email-jingchang.lu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(189002)(199003)(104016003)(31966008)(90102001)(77156001)(33646002)(76482002)(105606002)(76176999)(102836001)(2351001)(2371004)(229853001)(85306004)(62966002)(50466002)(99396002)(97736003)(85852003)(83072002)(107046002)(68736004)(26826002)(36756003)(74662003)(46102003)(74502003)(80022003)(81342003)(81542003)(110136001)(77982003)(69596002)(79102003)(86362001)(104166001)(47776003)(50226001)(21056001)(81156004)(92726001)(83322001)(19580395003)(19580405001)(88136002)(44976005)(575784001)(93916002)(92566001)(48376002)(89996001)(50986999)(20776003)(84676001)(4396001)(95666004)(6806004)(87286001)(106466001)(64706001)(87936001)(120916001)(2004002); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR03MB173; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY2PR03MB173; X-Forefront-PRVS: 034215E98F Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=jingchang.lu@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140922_013933_679717_A98C3AC9 X-CRM114-Status: GOOD ( 10.26 ) X-Spam-Score: -0.3 (/) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Chao Fu , arnd@arndb.de, Alison Wang , Bhupesh Sharma , Xiubo Li , Jason Jin , Jingchang Lu , Jingchang Lu , linux-arm-kernel@lists.infradead.org, Jaiprakash Singh X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jingchang Lu Signed-off-by: Alison Wang Signed-off-by: Chao Fu Signed-off-by: Jason Jin Signed-off-by: Xiubo Li Signed-off-by: Bhupesh Sharma Signed-off-by: Jaiprakash Singh Signed-off-by: Jingchang Lu --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/ls1021a-qds.dts | 285 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 286 insertions(+) create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e12fe46..384aa74 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -245,6 +245,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-tx6q-1110.dtb \ imx6sl-evk.dtb \ imx6sx-sdb.dtb \ + ls1021a-qds.dtb \ vf610-colibri-eval-v3.dtb \ vf610-cosmic.dtb \ vf610-twr.dtb diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts new file mode 100644 index 0000000..a0a95f51 --- /dev/null +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -0,0 +1,285 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A QDS Board"; + + aliases { + enet0_rgmii_phy = &rgmii_phy1; + enet1_rgmii_phy = &rgmii_phy2; + enet2_rgmii_phy = &rgmii_phy3; + enet0_sgmii_phy = &sgmii_phy1c; + enet1_sgmii_phy = &sgmii_phy1d; + }; + + soc { + leds { + compatible = "pwm-leds"; + led0 { + label = "led0"; + pwms = <&pwm3 0 150000 0>; + max-brightness = <100>; + }; + led1 { + label = "led1"; + pwms = <&pwm3 1 150000 0>; + max-brightness = <100>; + }; + led2 { + label = "led2"; + pwms = <&pwm3 2 150000 0>; + max-brightness = <100>; + }; + led3 { + label = "led3"; + pwms = <&pwm3 3 150000 0>; + max-brightness = <100>; + }; + led4 { + label = "led4"; + pwms = <&pwm3 4 150000 0>; + max-brightness = <100>; + }; + led5 { + label = "led5"; + pwms = <&pwm3 5 150000 0>; + max-brightness = <100>; + }; + led6 { + label = "led6"; + pwms = <&pwm3 6 150000 0>; + max-brightness = <100>; + }; + led7 { + label = "led7"; + pwms = <&pwm3 7 150000 0>; + max-brightness = <100>; + }; + }; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dspiflash: at45db021d@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&enet0 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy1c>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy1d>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy3>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "philips,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + interrupts = ; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adt7461a"; + reg = <0x4c>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; +}; + +&ifc { + status = "okay"; + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ifc-nand"; + reg = <0x2 0x0 0x10000>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1[2:0] */ + + /* Onboard PHYs */ + ls1021amdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + ls1021amdio1: mdio@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + ls1021amdio2: mdio@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + ls1021amdio3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1c: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + ls1021amdio4: mdio@80 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1d: ethernet-phy@1d { + reg = <0x1d>; + }; + }; + }; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + tbi0: tbi-phy@8 { + reg = <0x8>; + device_type = "tbi-phy"; + }; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +};