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Wed, 24 Sep 2014 12:47:10 +0900 (KST) From: Thomas Abraham To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v10 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property Date: Wed, 24 Sep 2014 09:27:55 +0530 Message-id: <1411531078-10671-4-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1411531078-10671-3-git-send-email-thomas.ab@samsung.com> References: <1411531078-10671-1-git-send-email-thomas.ab@samsung.com> <1411531078-10671-2-git-send-email-thomas.ab@samsung.com> <1411531078-10671-3-git-send-email-thomas.ab@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsWyRsSkTnefnVKIwb99ChbNm4otrn95zmpx dtlBNov/j16zWhz9XWDRu+Aqm8Wbh5sZLTY9vsZq8bn3CKPFjPP7mCyeTrjIZnHyTy+jRccy RotVu/4wWmz86uHA7zG74SKLx9/n11k8ds66y+5x59oeNo/NS+o9+rasYvTYfm0es8fm09Ue nzfJBXBGcdmkpOZklqUW6dslcGVM+qVacMii4saBl+wNjH+1uxg5OSQETCR+HHvMAmGLSVy4 t56ti5GLQ0hgKaPEn0vbmWCKHly8D5WYziixc0YLE4TTxiQxbf1NsHY2AR2JG29+M4LYIgJO Et+OXAMrYhaYzCxx6MAVoAQHh7BAmMS1j1ogNSwCqhIHXrSBbeAVcJX4dOk2K8Q2JYkNvUfB 4pwCbhLTpuwHmykksJdR4tECPZCZEgIv2SUO321ngxgkIPFt8iEWkPkSArISmw4wQ8yRlDi4 4gbLBEbhBYwMqxhFUwuSC4qT0otM9IoTc4tL89L1kvNzNzECY+r0v2cTdjDeO2B9iFGAg1GJ h3eCuFKIEGtiWXFl7iFGU6ANE5mlRJPzgZGbVxJvaGxmZGFqYmpsZG5ppiTO+1rqZ7CQQHpi SWp2ampBalF8UWlOavEhRiYOTqkGRjnPKvbds1aLZ83Psy89qGKt/eqarvAFIZvHObNW/Vt3 VvN6/JxdUuqH3vz5ftfHyiZmURZvtzZvbmMKR8eHWHuLQ5sYshUUVqul1VptfFitZGDyzcZO P2VWMX/j4/OfHBJyZ6oxON72C69zMg5P3PHT0zeB6ZV1aXVuZZwMM79vhG1f+y0lluKMREMt 5qLiRABRi75opAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNIsWRmVeSWpSXmKPExsVy+t9jQd19dkohBqcmi1o0byq2uP7lOavF 2WUH2Sz+P3rNanH0d4FF74KrbBZvHm5mtNj0+BqrxefeI4wWM87vY7J4OuEim8XJP72MFh3L GC1W7frDaLHxq4cDv8fshossHn+fX2fx2DnrLrvHnWt72Dw2L6n36NuyitFj+7V5zB6bT1d7 fN4kF8AZ1cBok5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6kkJeYm2qr5OIToOuW mQN0vZJCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsIYxY9Iv1YJDFhU3Drxk b2D8q93FyMkhIWAi8eDifTYIW0ziwr31QDYXh5DAdEaJnTNamCCcNiaJaetvsoBUsQnoSNx4 85sRxBYRcJL4duQaWBGzwGRmiUMHrgAlODiEBcIkrn3UAqlhEVCVOPCijQnE5hVwlfh06TYr xDYliQ29R8HinAJuEtOm7AebKSSwl1Hi0QK9CYy8CxgZVjGKphYkFxQnpeca6hUn5haX5qXr JefnbmIER+wzqR2MKxssDjEKcDAq8fBOEFcKEWJNLCuuzD3EKMHBrCTCu08VKMSbklhZlVqU H19UmpNafIjRFOiqicxSosn5wGSSVxJvaGxibmpsamliYWJmqSTOe6DVOlBIID2xJDU7NbUg tQimj4mDU6qBUXLucenO3zWxauoTLOdcMDedPfPN/j2q9/1Oi7pdPMgVEn7D7MeukPo3N6vX Oh4LzD257uxLFf81BlwR0kciGqNt7x4+JB1w8Pa+xRu4b7Ttfva5JvPposmf9zrt6V1+iYtp Wlbb/JIvTuLRZRVGTv+z5qSs5a9Z6ayvEOTWvuez7upZknt6E5VYijMSDbWYi4oTAeRJHUTu AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140923_204744_281653_72FC5C97 X-CRM114-Status: UNSURE ( 9.74 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -5.7 (-----) Cc: l.majewski@samsung.com, kgene.kim@samsung.com, mturquette@linaro.org, heiko@sntech.de, Sachin Kamat , viresh.kumar@linaro.org, tomasz.figa@gmail.com, Doug Anderson , cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com, Andreas Faerber , Javier Martinez Canillas X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq drivers. Cc: Kukjin Kim Cc: Doug Anderson Cc: Javier Martinez Canillas Cc: Andreas Faerber Cc: Sachin Kamat Signed-off-by: Thomas Abraham Reviewed-by: Andreas Farber Tested-by: Javier Martinez Canillas Tested-by: Chander Kashyap --- arch/arm/boot/dts/exynos4210-origen.dts | 4 ++ arch/arm/boot/dts/exynos4210-trats.dts | 4 ++ arch/arm/boot/dts/exynos4210-universal_c210.dts | 4 ++ arch/arm/boot/dts/exynos4210.dtsi | 14 ++++++++- arch/arm/boot/dts/exynos5250-arndale.dts | 4 ++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 ++ arch/arm/boot/dts/exynos5250-snow.dts | 4 ++ arch/arm/boot/dts/exynos5250.dtsi | 25 ++++++++++++++- arch/arm/boot/dts/exynos5420.dtsi | 38 +++++++++++++++++++++++ 9 files changed, 99 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index f767c42..887dded 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -334,3 +334,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&buck1_reg>; +}; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index f516da9..66119dd 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -446,3 +446,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&varm_breg>; +}; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d50eb3a..bf0a39c 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -492,3 +492,7 @@ &mdma1 { reg = <0x12840000 0x1000>; }; + +&cpu0 { + cpu0-supply = <&vdd_arm_reg>; +}; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index bcc9e63..69bac07 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -35,10 +35,22 @@ #address-cells = <1>; #size-cells = <0>; - cpu@900 { + cpu0: cpu@900 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x900>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <160000>; + + operating-points = < + 1200000 1250000 + 1000000 1150000 + 800000 1075000 + 500000 975000 + 400000 975000 + 200000 950000 + >; }; cpu@901 { diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 3acd97e..da2b3e1 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -563,3 +563,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 6a0f4c0..0eedb88 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -406,3 +406,7 @@ }; }; }; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index e51fcef..f954e82 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -624,4 +624,8 @@ num-cs = <1>; }; +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + #include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index f21b9aa..d4b418e 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -58,11 +58,34 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1700000000>; + + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + clock-latency = <140000>; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; }; cpu@1 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index bfe056d..912deeb 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -59,8 +59,26 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu-cluster.0"; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + clock-latency = <140000>; + + operating-points = < + 1800000 1250000 + 1700000 1212500 + 1600000 1175000 + 1500000 1137500 + 1400000 1112500 + 1300000 1062500 + 1200000 1037500 + 1100000 1012500 + 1000000 987500 + 900000 962500 + 800000 937500 + 700000 912500 + >; }; cpu1: cpu@1 { @@ -69,6 +87,7 @@ reg = <0x1>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + clock-latency = <140000>; }; cpu2: cpu@2 { @@ -77,6 +96,7 @@ reg = <0x2>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + clock-latency = <140000>; }; cpu3: cpu@3 { @@ -85,14 +105,29 @@ reg = <0x3>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + clock-latency = <140000>; }; cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; + clock-names = "cpu-cluster.1"; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + clock-latency = <140000>; + + operating-points = < + 1300000 1275000 + 1200000 1212500 + 1100000 1162500 + 1000000 1112500 + 900000 1062500 + 800000 1025000 + 700000 975000 + 600000 937500 + >; }; cpu5: cpu@101 { @@ -101,6 +136,7 @@ reg = <0x101>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + clock-latency = <140000>; }; cpu6: cpu@102 { @@ -109,6 +145,7 @@ reg = <0x102>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + clock-latency = <140000>; }; cpu7: cpu@103 { @@ -117,6 +154,7 @@ reg = <0x103>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + clock-latency = <140000>; }; };