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Wed, 24 Sep 2014 12:47:18 +0900 (KST) From: Thomas Abraham To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v10 6/6] clk: samsung: remove unused clock aliases and update clock flags Date: Wed, 24 Sep 2014 09:27:58 +0530 Message-id: <1411531078-10671-7-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1411531078-10671-6-git-send-email-thomas.ab@samsung.com> References: <1411531078-10671-1-git-send-email-thomas.ab@samsung.com> <1411531078-10671-2-git-send-email-thomas.ab@samsung.com> <1411531078-10671-3-git-send-email-thomas.ab@samsung.com> <1411531078-10671-4-git-send-email-thomas.ab@samsung.com> <1411531078-10671-5-git-send-email-thomas.ab@samsung.com> <1411531078-10671-6-git-send-email-thomas.ab@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsWyRsSkVveYnVKIwfE/VhbXvzxntfj/6DWr Re+Cq2wWbx5uZrTY9Pgaq8Xn3iOMFjPO72OyeDrhIptFxzJGi1W7/jBabPzq4cDtsXPWXXaP O9f2sHlsXlLv0bdlFaPH9mvzmD0+b5ILYIvisklJzcksSy3St0vgynhzdwZzwRfvii0LN7A0 MN5x6GLk5JAQMJFov/ydGcIWk7hwbz1bFyMXh5DAUkaJabs2MMEUXTi4mB0iMZ1RYnXLVrAO IYE2Jokz0xNBbDYBHYkbb34zgtgiAk4S345cYwJpYBZ4wCixcVETO0hCWCBa4lnDUVYQm0VA VWL31MNgDbwCrhKbrl9ihNimJLGh9yjYZk4BN4n19+5DnfSRSeLmp/usII6EwD52iQNvpjFD TBKQ+Db5EEsXIwdQQlZi0wGofyQlDq64wTKBUXgBI8MqRtHUguSC4qT0ImO94sTc4tK8dL3k /NxNjMC4OP3vWf8OxrsHrA8xCnAwKvHwThBXChFiTSwrrsw9xGgKtGEis5Rocj4w+vJK4g2N zYwsTE1MjY3MLc2UxHkXSv0MFhJITyxJzU5NLUgtii8qzUktPsTIxMEp1cC4Y+PiTllT9Z33 /GLt8gSn/dsr0W/hE+Wm+vmggST7PN2jNxj7e92m3jvw5slKl/zbRzIuWmXy+6w/JHh8zpxZ a5M0T/a2/1dl5SjPeBi3+yLLiklv37dOeNmzkN3x8KdF36dZW264Y//O5GTJSdljsdU2vtEp rZdWMjx57bLef7ORjm7LtaxQJZbijERDLeai4kQAMCOQWIYCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLIsWRmVeSWpSXmKPExsVy+t9jQd1jdkohBotOG1hc//Kc1eL/o9es Fr0LrrJZvHm4mdFi0+NrrBafe48wWsw4v4/J4umEi2wWHcsYLVbt+sNosfGrhwO3x85Zd9k9 7lzbw+axeUm9R9+WVYwe26/NY/b4vEkugC2qgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTM wFDX0NLCXEkhLzE31VbJxSdA1y0zB+g6JYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFw PUYGaCBhDWPGm7szmAu+eFdsWbiBpYHxjkMXIyeHhICJxIWDi9khbDGJC/fWs3UxcnEICUxn lFjdspUZJCEk0MYkcWZ6IojNJqAjcePNb0YQW0TASeLbkWtMIA3MAg8YJTYuagKbJCwQLfGs 4SgriM0ioCqxe+phsAZeAVeJTdcvMUJsU5LY0HuUCcTmFHCTWH/vPtTmj0wSNz/dZ53AyLuA kWEVo2hqQXJBcVJ6rqFecWJucWleul5yfu4mRnDUPZPawbiyweIQowAHoxIP7wRxpRAh1sSy 4srcQ4wSHMxKIrz7VIFCvCmJlVWpRfnxRaU5qcWHGE2BzprILCWanA9MCHkl8YbGJuamxqaW JhYmZpZK4rwHWq0DhQTSE0tSs1NTC1KLYPqYODilGhh3XnP7ptEV7DY5T3myn/c0p3ctp/3t lk2exGS+QFc9743K82sCizyZZO//2inL6iLxoa6ubeOvBXO1tt6WXZS26eCb7H/T1VzjDzZc nXI88ErdZmv7WcFWi1gZOA65FrZ0mAUvbt2RIlal6jivpk+vRoLDT97JaG/spqa13+XnXn+p NVGG8YISS3FGoqEWc1FxIgBap+zB0AIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140923_204731_131569_3D5E6957 X-CRM114-Status: GOOD ( 10.83 ) X-Spam-Score: -5.7 (-----) Cc: l.majewski@samsung.com, kgene.kim@samsung.com, mturquette@linaro.org, heiko@sntech.de, viresh.kumar@linaro.org, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With some of the Exynos SoCs switched over to use the generic CPUfreq drivers, the unused clock aliases can be removed. In addition to this, the individual clock blocks which are now encapsulated with the consolidate CPU clock type can now be marked with read-only flags. Cc: Tomasz Figa Signed-off-by: Thomas Abraham Acked-by: Viresh Kumar Acked-by: Mike Turquette Tested-by: Javier Martinez Canillas Tested-by: Chander Kashyap --- drivers/clk/samsung/clk-exynos4.c | 48 +++++++++++++++++----------------- drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++----- drivers/clk/samsung/clk-exynos5420.c | 27 ++++++++++++------ 3 files changed, 53 insertions(+), 41 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 101f549..04619a1 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), - MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), + MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, 0, + CLK_MUX_READ_ONLY), MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1), MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), @@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus", CLKOUT_CMU_RIGHTBUS, 8, 6), - DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), - DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3), - DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3), - DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3), - DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3), - DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3), - DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3), - DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), - DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3), + DIV_F(0, "div_core", "mout_core", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_periph", "div_core2", DIV_CPU0, 12, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_atb", "mout_core", DIV_CPU0, 16, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6), DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), @@ -770,7 +780,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), - DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), + DIV_F(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, CLK_SET_RATE_PARENT, 0), DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, @@ -1187,17 +1198,10 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 0), }; -static struct samsung_clock_alias exynos4_aliases[] __initdata = { +static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), ALIAS(CLK_ARM_CLK, NULL, "armclk"), ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"), -}; - -static struct samsung_clock_alias exynos4210_aliases[] __initdata = { - ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"), -}; - -static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"), }; @@ -1464,8 +1468,6 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4210_div_clks)); samsung_clk_register_gate(ctx, exynos4210_gate_clks, ARRAY_SIZE(exynos4210_gate_clks)); - samsung_clk_register_alias(ctx, exynos4210_aliases, - ARRAY_SIZE(exynos4210_aliases)); samsung_clk_register_fixed_factor(ctx, exynos4210_fixed_factor_clks, ARRAY_SIZE(exynos4210_fixed_factor_clks)); @@ -1487,9 +1489,6 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); } - samsung_clk_register_alias(ctx, exynos4_aliases, - ARRAY_SIZE(exynos4_aliases)); - exynos4_core_down_clock(soc); exynos4_clk_sleep_init(); @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", _get_rate("sclk_apll"), _get_rate("sclk_mpll"), _get_rate("sclk_epll"), _get_rate("sclk_vpll"), + exynos4_soc == EXYNOS4210 ? _get_rate("armclk") : _get_rate("div_core2")); } diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index e19e365..1d958f1 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -291,14 +291,14 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { /* * CMU_CPU */ - MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, - CLK_SET_RATE_PARENT, 0, "mout_apll"), - MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), + MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, CLK_MUX_READ_ONLY), /* * CMU_CORE */ - MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), + MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), /* * CMU_TOP @@ -380,9 +380,12 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { /* * CMU_CPU */ - DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), - DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), - DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), + DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), /* * CMU_TOP @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_of_add_provider(np, ctx); pr_info("Exynos5250: clock setup completed, armclk=%ld\n", - _get_rate("div_arm2")); + _get_rate("armclk")); } CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index d7ef36a..fcf365d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -617,10 +617,14 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), - MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), - MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), - MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), - MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), + MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, + CLK_MUX_READ_ONLY), + MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1, 0, + CLK_MUX_READ_ONLY), MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), @@ -776,11 +780,16 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { }; static struct samsung_div_clock exynos5x_div_clks[] __initdata = { - DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), - DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), - DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), - DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), - DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), + DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "armclk2", "div_arm", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),