From patchwork Sat Sep 27 04:58:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Dubey X-Patchwork-Id: 4988901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 210DF9F1D4 for ; Sat, 27 Sep 2014 05:08:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 394612022A for ; Sat, 27 Sep 2014 05:08:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3B435201F7 for ; Sat, 27 Sep 2014 05:08:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XXkB5-00044s-Fu; Sat, 27 Sep 2014 05:04:15 +0000 Received: from mailout3.samsung.com ([203.254.224.33]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XXkAw-00042S-G6 for linux-arm-kernel@lists.infradead.org; Sat, 27 Sep 2014 05:04:07 +0000 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NCJ006EMNE6U840@mailout3.samsung.com> for linux-arm-kernel@lists.infradead.org; Sat, 27 Sep 2014 14:03:42 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 54.A9.17016.E2546245; Sat, 27 Sep 2014 14:03:42 +0900 (KST) X-AuditID: cbfee68d-f79296d000004278-a7-5426452e8941 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id F2.40.20081.E2546245; Sat, 27 Sep 2014 14:03:42 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NCJ00HUDNDYOEA0@mmp2.samsung.com>; Sat, 27 Sep 2014 14:03:42 +0900 (KST) From: Pankaj Dubey To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/2] clk: samsung: exynos3250: add uart2/3 related clocks Date: Sat, 27 Sep 2014 10:28:47 +0530 Message-id: <1411793928-32692-2-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1411793928-32692-1-git-send-email-pankaj.dubey@samsung.com> References: <1411793928-32692-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrILMWRmVeSWpSXmKPExsWyRsSkRlfPVS3E4PQUXYveBVfZLDY9vsZq MeP8PiaL25d5LZ5OuMhm8enof1aLRVu/sFu07j3CbnH4TTurxapdfxgduDxamnvYPHbOusvu sWlVJ5vHnWt72Dw2L6n36NuyitHj8ya5APYoLpuU1JzMstQifbsEroxNq/cyFZxWrtgw/zJr A+Mb2S5GTg4JAROJcwfOsEHYYhIX7q0Hsrk4hASWMko0tK5i6mLkACs60q4OEZ/OKLF1/gNm CGcCk8S0xnZmkG42AV2JJ+/nMoM0iAh4Syy/pghSwyzwnVFi5sxNYBuEBTwl/k5/yQ5iswio SkxeNIcFxOYV8JCYM6WbBWKZgsScSTYgYU6g8oZTC8FKhIBK1i5dww4yU0JgH7vEzo+zWCDm CEh8m3wIqldWYtMBZohnJCUOrrjBMoFReAEjwypG0dSC5ILipPQiQ73ixNzi0rx0veT83E2M wJg4/e9Z7w7G2wesDzEKcDAq8fCeEFcLEWJNLCuuzD3EaAq0YSKzlGhyPjDy8kriDY3NjCxM TUyNjcwtzZTEeRWlfgYLCaQnlqRmp6YWpBbFF5XmpBYfYmTi4JRqYGx+NunzYou0vg2aXjf3 Tpr2h/3gSesjAm9FnJedVS0qDWR4w5l5pnBbWOJ3tvLfli90D76OWZvixjV7XXHw79PsbP7X 7U4WhW64xqQvtLagyH6aZ53QqpuLFjqvS41vO1rw7MpmPvsLsst8+jff4ZL4krlmy73Je/dV fb58pog5sChi9fQnF8uVWIozEg21mIuKEwGogyfKhAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNIsWRmVeSWpSXmKPExsVy+t9jQV09V7UQgwkHVS16F1xls9j0+Bqr xYzz+5gsbl/mtXg64SKbxaej/1ktFm39wm7RuvcIu8XhN+2sFqt2/WF04PJoae5h89g56y67 x6ZVnWwed67tYfPYvKTeo2/LKkaPz5vkAtijGhhtMlITU1KLFFLzkvNTMvPSbZW8g+Od403N DAx1DS0tzJUU8hJzU22VXHwCdN0yc4DOU1IoS8wpBQoFJBYXK+nbYZoQGuKmawHTGKHrGxIE 12NkgAYS1jBmbFq9l6ngtHLFhvmXWRsY38h2MXJwSAiYSBxpV+9i5AQyxSQu3FvP1sXIxSEk MJ1RYuv8B8wQzgQmiWmN7cwgVWwCuhJP3s9lBmkWEfCWWH5NEaSGWeA7o8TMmZvYQGqEBTwl /k5/yQ5iswioSkxeNIcFxOYV8JCYM6WbBWKxgsScSTYgYU6g8oZTC8FKhIBK1i5dwz6BkXcB I8MqRtHUguSC4qT0XEO94sTc4tK8dL3k/NxNjOCIeya1g3Flg8UhRgEORiUe3gJRtRAh1sSy 4srcQ4wSHMxKIrw2XEAh3pTEyqrUovz4otKc1OJDjKZAR01klhJNzgcmg7ySeENjE3NTY1NL EwsTM0slcd4DrdaBQgLpiSWp2ampBalFMH1MHJxSDYxOkQKpN6dKNwVuSd3LH/Bjaejehbkv AsUWW3y+92SvJlcpB1P3enllk3N2364YLOkINkrzsNPccs7je8zcqb8TZRKY5fi7H335GlC5 dMfvgtWhVb3nevZ8O+8cIST2gmMd50ZRjmsGXRFGhw0efcvqMZvMNyFl34Wjhr5R89u0luge VJ6R80CJpTgj0VCLuag4EQC2gHW8zgIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140926_220406_689868_E564FAEF X-CRM114-Status: UNSURE ( 8.27 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -5.7 (-----) Cc: kgene.kim@samsung.com, linux@arm.linux.org.uk, naushad@samsung.com, Pankaj Dubey , tomasz.figa@gmail.com, robh+dt@kernel.org, Sylwester Nawrocki , Mike Turquette X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos3250 has four UART channels UART0,1,2 and 3. This patch adds missing clock entries for UART2 and UART3. CC: Mike Turquette CC: Sylwester Nawrocki Signed-off-by: Pankaj Dubey --- drivers/clk/samsung/clk-exynos3250.c | 11 +++++++++++ include/dt-bindings/clock/exynos3250.h | 10 +++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index dc85f8e..0722fef 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -357,6 +357,8 @@ static struct samsung_mux_clock mux_clks[] __initdata = { MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3), /* SRC_PERIL0 */ + MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4), + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4), MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), @@ -439,6 +441,8 @@ static struct samsung_div_clock div_clks[] __initdata = { DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), /* DIV_PERIL0 */ + DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), @@ -601,6 +605,10 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3", + GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -679,6 +687,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0), GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), @@ -698,6 +707,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), + GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0), + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0), GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), }; diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index b535e9d..ffeb695 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -78,6 +78,8 @@ #define CLK_MOUT_CORE 58 #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 +#define CLK_MOUT_UART2 61 +#define CLK_MOUT_UART3 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -126,6 +128,8 @@ #define CLK_DIV_CORE 107 #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 +#define CLK_DIV_UART2 110 +#define CLK_DIV_UART3 111 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -222,6 +226,8 @@ #define CLK_BLOCK_MFC 219 #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 +#define CLK_UART2 222 +#define CLK_UART3 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -248,11 +254,13 @@ #define CLK_SCLK_SPI0 245 #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 +#define CLK_SCLK_UART2 248 +#define CLK_SCLK_UART3 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 248 +#define CLK_NR_CLKS 250 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */