From patchwork Sat Sep 27 11:25:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joachim Eastwood X-Patchwork-Id: 4989771 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DF0B59F1D4 for ; Sat, 27 Sep 2014 11:30:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B206120200 for ; Sat, 27 Sep 2014 11:30:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B6673201FB for ; Sat, 27 Sep 2014 11:30:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XXq8v-0001Lq-DS; Sat, 27 Sep 2014 11:26:25 +0000 Received: from mail-lb0-x235.google.com ([2a00:1450:4010:c04::235]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XXq8s-0001Jd-Up for linux-arm-kernel@lists.infradead.org; Sat, 27 Sep 2014 11:26:23 +0000 Received: by mail-lb0-f181.google.com with SMTP id n15so1427448lbi.40 for ; Sat, 27 Sep 2014 04:25:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=I4I0sANyD13clpnsRqCtoA7lDD4t1nd3VYXDSIbLPrc=; b=msEkH+om3cNbi5r3vhAJtE0N0McP/rYUqXZTWfHo6998qD/0mFyq6ICWlHdDUPwmZz +mzN1Yaq7OhjqK/3p6njdVKx7mtndck2kt89mMXXC5NoAH3Xld53tUNluY27LHOFEJcR o1NfWwLA94LZjBdnvKVCm4iyHBdkBG5tsPRq1VIuPkcQa0QPRgJqFrUDHrvg295fDTAb PoaufI62spjrh+hHgdc7ydoOuCdXB1R8W2Z2oNNrFcVKwCpFnAj1saV3mqHl93o3uw0i SMYQ8g9bTZUUf1KtZFVbyuxadSmiVJGt4g2n+mlUCFuxPSvr1u6cvYa5dtTCIp0zsg1v Rzew== X-Received: by 10.152.206.101 with SMTP id ln5mr26481434lac.46.1411817159242; Sat, 27 Sep 2014 04:25:59 -0700 (PDT) Received: from localhost.localdomain ([90.149.48.183]) by mx.google.com with ESMTPSA id ad3sm1781651lbc.45.2014.09.27.04.25.58 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 27 Sep 2014 04:25:58 -0700 (PDT) From: Joachim Eastwood To: arnd@arndb.de, linux@arm.linux.org.uk, catalin.marinas@arm.com, u.kleine-koenig@pengutronix.de Subject: =?UTF-8?q?=5BPATCH=20v4=5D=20ARM=3A=20zImage=3A=20add=20support=20for=20ARMv7-M?= Date: Sat, 27 Sep 2014 13:25:49 +0200 Message-Id: <1411817149-5135-1-git-send-email-manabian@gmail.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1411057343-20861-1-git-send-email-manabian@gmail.com> References: <1411057343-20861-1-git-send-email-manabian@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140927_042623_179008_3CDA931A X-CRM114-Status: GOOD ( 13.68 ) X-Spam-Score: -0.1 (/) Cc: Joachim Eastwood , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch makes it possible to enter zImage in Thumb mode for ARMv7M (Cortex-M) CPUs that does not support ARM mode. The kernel entry is also made in Thumb mode. Signed-off-by: Joachim Eastwood --- Hi, Updated patch with comments from Uwe Kleine-König. Changes v4: Preserve r1/r2. Add comment about class A/R. v3: Use defines for ARMv7M CPU registers. v2: Introduce AR_CLASS/M_CLASS macros. This reduces the amount of ifdefs needed in compressed/head.S. Successfully tested on NXP LPC4357 (Cortex-M4). regards, Joachim Eastwood arch/arm/boot/compressed/head.S | 28 ++++++++++++++++++++++------ arch/arm/include/asm/unified.h | 8 ++++++++ 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 413fd94b5301..0afcbb1e1d7d 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -10,8 +10,11 @@ */ #include #include +#include + + AR_CLASS( .arch armv7-a ) + M_CLASS( .arch armv7-m ) - .arch armv7-a /* * Debugging stuff * @@ -114,7 +117,12 @@ * sort out different calling conventions */ .align - .arm @ Always enter in ARM state + /* + * Always enter in ARM state for CPUs that support the ARM ISA. + * As of today (2014) that's exactly the members of the A and R + * classes. + */ + AR_CLASS( .arm ) start: .type start,#function .rept 7 @@ -132,14 +140,15 @@ start: THUMB( .thumb ) 1: - ARM_BE8( setend be ) @ go BE8 if compiled for BE8 - mrs r9, cpsr + ARM_BE8( setend be ) @ go BE8 if compiled for BE8 + AR_CLASS( mrs r9, cpsr ) #ifdef CONFIG_ARM_VIRT_EXT bl __hyp_stub_install @ get into SVC mode, reversibly #endif mov r7, r1 @ save architecture ID mov r8, r2 @ save atags pointer +#ifndef CONFIG_CPU_V7M /* * Booting from Angel - need to enter SVC mode and disable * FIQs/IRQs (numeric definitions from angel arm.h source). @@ -155,6 +164,7 @@ not_angel: safe_svcmode_maskall r0 msr spsr_cxsf, r9 @ Save the CPU boot mode in @ SPSR +#endif /* * Note that some cache flushing and other stuff may * be needed here - is there an Angel SWI call for this? @@ -790,6 +800,9 @@ __common_mmu_cache_on: call_cache_fn: adr r12, proc_types #ifdef CONFIG_CPU_CP15 mrc p15, 0, r9, c0, c0 @ get processor ID +#elif defined(CONFIG_CPU_V7M) + ldr r9, =BASEADDR_V7M_SCB + ldr r9, [r9, V7M_SCB_CPUID] #else ldr r9, =CONFIG_PROCESSOR_ID #endif @@ -945,11 +958,13 @@ proc_types: W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush +#ifndef CONFIG_CPU_V7M .word 0x000f0000 @ new CPU Id .word 0x000f0000 W(b) __armv7_mmu_cache_on W(b) __armv7_mmu_cache_off W(b) __armv7_mmu_cache_flush +#endif .word 0 @ unrecognised type .word 0 @@ -1277,8 +1292,9 @@ __hyp_reentry_vectors: __enter_kernel: mov r0, #0 @ must be 0 - ARM( mov pc, r4 ) @ call kernel - THUMB( bx r4 ) @ entry point is always ARM + ARM( mov pc, r4 ) @ call kernel + M_CLASS( add r4, r4, #1 ) @ enter in Thumb mode for M class + THUMB( bx r4 ) @ entry point is always ARM for A/R classes reloc_code_end: diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h index b88beaba6b4a..200f9a7cd623 100644 --- a/arch/arm/include/asm/unified.h +++ b/arch/arm/include/asm/unified.h @@ -24,6 +24,14 @@ .syntax unified #endif +#ifdef CONFIG_CPU_V7M +#define AR_CLASS(x...) +#define M_CLASS(x...) x +#else +#define AR_CLASS(x...) x +#define M_CLASS(x...) +#endif + #ifdef CONFIG_THUMB2_KERNEL #if __GNUC__ < 4