diff mbox

[v2,3/3] ARM: dts: hix5hd2: add i2c node

Message ID 1411878129-19743-4-git-send-email-zhangfei.gao@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

Zhangfei Gao Sept. 28, 2014, 4:22 a.m. UTC
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
 arch/arm/boot/dts/hisi-x5hd2.dtsi |   60 +++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

Comments

Arnd Bergmann Sept. 30, 2014, 9:02 a.m. UTC | #1
On Sunday 28 September 2014 12:22:09 Zhangfei Gao wrote:
> +
> +               i2c0: i2c@b10000 {
> +                       compatible = "hisilicon,hix5hd2-i2c";
> +                       reg = <0xb10000 0x1000>;
> +                       interrupts = <0 38 4>;
> +                       clocks = <&clock HIX5HD2_I2C0_RST>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> 

HIX5HD2_I2C0_RST is not defined anywhere, so this will result in the
same build error that has required reverting a lot of patches for the
3.18 merge window.

How do you plan to deal with the dependency in the future?

	Arnd
Zhangfei Gao Sept. 30, 2014, 9:21 a.m. UTC | #2
On 09/30/2014 05:02 PM, Arnd Bergmann wrote:
> On Sunday 28 September 2014 12:22:09 Zhangfei Gao wrote:
>> +
>> +               i2c0: i2c@b10000 {
>> +                       compatible = "hisilicon,hix5hd2-i2c";
>> +                       reg = <0xb10000 0x1000>;
>> +                       interrupts = <0 38 4>;
>> +                       clocks = <&clock HIX5HD2_I2C0_RST>;
>> +                       #address-cells = <1>;
>> +                       #size-cells = <0>;
>> +                       status = "disabled";
>> +               };
>>
>
> HIX5HD2_I2C0_RST is not defined anywhere, so this will result in the
> same build error that has required reverting a lot of patches for the
> 3.18 merge window.
>
> How do you plan to deal with the dependency in the future?
>

HIX5HD2_I2C0_RST in clock patch and already been merged through clock 
tree in 09/29, should be in 3.18-rc1 (not sure).
When clock patch are combined in the same rc, will send the dts patch.
Sorry for the build issue.

Thanks
Wei Xu Sept. 30, 2014, 9:31 a.m. UTC | #3
On 2014/9/30 17:02, Arnd Bergmann wrote:
> On Sunday 28 September 2014 12:22:09 Zhangfei Gao wrote:
>> +
>> +               i2c0: i2c@b10000 {
>> +                       compatible = "hisilicon,hix5hd2-i2c";
>> +                       reg = <0xb10000 0x1000>;
>> +                       interrupts = <0 38 4>;
>> +                       clocks = <&clock HIX5HD2_I2C0_RST>;
>> +                       #address-cells = <1>;
>> +                       #size-cells = <0>;
>> +                       status = "disabled";
>> +               };
>>

Hi Arnd,
 
> HIX5HD2_I2C0_RST is not defined anywhere, so this will result in the
> same build error that has required reverting a lot of patches for the
> 3.18 merge window.

Sorry again for bringing so much troubles to you, Olof and Stephen.
On 9/30, Mike Turquette has already accepted the clock pull request
which includes the HIX5HD2_I2C0_RST definition.

> How do you plan to deal with the dependency in the future? 

In the future, I will check the dependence firstly about the patches.
When creating pull request tag, I will test it and make sure it works.
And I will also make sure that the order of the pull request is sent correctly.

Best Regards,
Wei

> 	Arnd
> 
> .
>
diff mbox

Patch

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index d3d99fb..17d0637 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -476,5 +476,65 @@ 
                         interrupts = <0 70 4>;
                         clocks = <&clock HIX5HD2_SATA_CLK>;
 		};
+
+		i2c0: i2c@b10000 {
+			compatible = "hisilicon,hix5hd2-i2c";
+			reg = <0xb10000 0x1000>;
+			interrupts = <0 38 4>;
+			clocks = <&clock HIX5HD2_I2C0_RST>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@b11000 {
+			compatible = "hisilicon,hix5hd2-i2c";
+			reg = <0xb11000 0x1000>;
+			interrupts = <0 39 4>;
+			clocks = <&clock HIX5HD2_I2C1_RST>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@b12000 {
+			compatible = "hisilicon,hix5hd2-i2c";
+			reg = <0xb12000 0x1000>;
+			interrupts = <0 40 4>;
+			clocks = <&clock HIX5HD2_I2C2_RST>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@b13000 {
+			compatible = "hisilicon,hix5hd2-i2c";
+			reg = <0xb13000 0x1000>;
+			interrupts = <0 41 4>;
+			clocks = <&clock HIX5HD2_I2C3_RST>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@b16000 {
+			compatible = "hisilicon,hix5hd2-i2c";
+			reg = <0xb16000 0x1000>;
+			interrupts = <0 43 4>;
+			clocks = <&clock HIX5HD2_I2C4_RST>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@b17000 {
+			compatible = "hisilicon,hix5hd2-i2c";
+			reg = <0xb17000 0x1000>;
+			interrupts = <0 44 4>;
+			clocks = <&clock HIX5HD2_I2C5_RST>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 	};
 };