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[79.20.112.132]) by mx.google.com with ESMTPSA id a2sm8898533wic.19.2014.09.30.01.44.06 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 30 Sep 2014 01:44:07 -0700 (PDT) From: Carlo Caione To: robh+dt@kernel.org, mark.rutland@arm.com, linux@arm.linux.org.uk, maxime.ripard@free-electrons.com, b.galvani@gmail.com, jerry.cao@amlogic.com, victor.wan@amlogic.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] ARM: Meson6: docs: document bindings Date: Tue, 30 Sep 2014 10:43:53 +0200 Message-Id: <1412066635-5298-2-git-send-email-carlo@caione.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1412066635-5298-1-git-send-email-carlo@caione.org> References: <1412066635-5298-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140930_014430_543928_BD8D477D X-CRM114-Status: GOOD ( 11.46 ) X-Spam-Score: -0.7 (/) Cc: Carlo Caione X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Documentation for the devicetree bindings introduced with the SMP support Signed-off-by: Carlo Caione --- .../bindings/arm/meson/amlogic,meson6-cpuconfig | 16 +++++++++++++ .../bindings/arm/meson/amlogic,meson6-smp | 26 ++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp diff --git a/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig b/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig new file mode 100644 index 0000000..2db4cbb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig @@ -0,0 +1,16 @@ +Secondary CPU management unit: +------------------------------- + +This document describes the "amlogic,meson6-cpuconfig" node for enabling the +secondary CPU. + +Required node properties: +- compatible value : = "amlogic,meson6-cpuconfig"; +- reg : physical base address and the size of the registers window + +Example: + + cpuconfig@d901ff80 { + compatible = "amlogic,meson6-cpuconfig"; + reg = <0xd901ff80 0x8>; + }; diff --git a/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp b/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp new file mode 100644 index 0000000..4130381 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp @@ -0,0 +1,26 @@ +Secondary CPU enable-method "amlogic,meson6-smp" binding: +---------------------------------------------------------- + +This document describes the "amlogic,meson6-smp" method for enabling secondary +CPUs. To apply to all CPUs, a single "amlogic,meson6-smp" enable method should +be defined in the "cpus" node. + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "amlogic,meson6-smp"; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x200>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x201>; + }; + };