From patchwork Tue Sep 30 14:59:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 5003881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AB2B2BEEA6 for ; Tue, 30 Sep 2014 15:02:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 668F2201C7 for ; Tue, 30 Sep 2014 15:02:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C2CD2018E for ; Tue, 30 Sep 2014 15:02:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XYytr-0004BV-JE; Tue, 30 Sep 2014 14:59:35 +0000 Received: from mail-pa0-x231.google.com ([2607:f8b0:400e:c03::231]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XYyto-000475-9p for linux-arm-kernel@lists.infradead.org; Tue, 30 Sep 2014 14:59:33 +0000 Received: by mail-pa0-f49.google.com with SMTP id lj1so3792369pab.22 for ; Tue, 30 Sep 2014 07:59:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=05itegbq5ihGch76gZDMTCa4VjN8N/uizRqUlN8T1xs=; b=btNN42phWIkJA1AiVjtj8aDn6u1Rj6qQTtWPBfk/VQImHwstpWi5ZS6kUkw8b7vfxw fwcT3dqO/MZ9AQ8aTc1TLM9UBdRmY5iz32QIsItJ6xCe5NjqKrYWQImWidynDPCEfct2 62PQ+PP5Jd76qKnv+HEhrkQGmF7BwGWXZ6FSKQM801eG6K35pMxZLOdje2z1QdKOME2r oVx67zT/FTEVpMQX2xyViYUOJq3yOAf7nyKW1U8Muvo5iVwd3SL7f6j2zuyWck7VwMei URmmosVFMINZXuzWB01e6QqruMGJvtTqz0lFnGIuJycMWyzDQh5+TKqyMYBpCGBPfH3P AHzA== X-Received: by 10.66.192.232 with SMTP id hj8mr28398963pac.117.1412089150813; Tue, 30 Sep 2014 07:59:10 -0700 (PDT) Received: from localhost.localdomain ([122.167.172.42]) by mx.google.com with ESMTPSA id nk11sm15450265pdb.40.2014.09.30.07.59.08 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 30 Sep 2014 07:59:10 -0700 (PDT) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v8] ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420 Date: Tue, 30 Sep 2014 20:29:02 +0530 Message-Id: <1412089142-12056-1-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 2.1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140930_075932_404755_8FAD8952 X-CRM114-Status: GOOD ( 26.73 ) X-Spam-Score: -0.7 (/) Cc: kgene.kim@samsung.com, javier@dowhile0.org, linux-samsung-soc@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use the MCPM layer to handle core suspend/resume on Exynos5420. Also, restore the entry address setup code post-resume. Signed-off-by: Abhilash Kesavan Acked-by: Nicolas Pitre --- Changes in v2: - Made use of the MCPM suspend/powered_up call-backs Changes in v3: - Used the residency value to indicate the entered state Changes in v4: - Checked if MCPM has been enabled to prevent build error Changes in v5: - Removed the MCPM flags and just used a local flag to indicate that we are suspending. Changes in v6: - Read the SYS_PWR_REG value to decide if we are suspending the system. - Restore the SYS_PWR_REG value post-resume. - Modified the comments to reflect the first change. Changes in v7: - Add the suspend check in exynos_cpu_power_down() rather than the MCPM back-end. - Clean-up unnecessary changes related to earlier versions. Changes in v8: - Rebased on the latest exynos PMU/PM support patches. This patch is based on kgene's for-next branch. http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next Here are the dependencies: 1) Decouple syscon interface from platform devices - v7 http://lkml.org/lkml/2014/9/30/156 2) ARM: Exynos: Convert PMU implementation into a platform driver - v8 http://www.spinics.net/lists/arm-kernel/msg366831.html 3) Exynos5420 PMU/S2R Series - v8 http://www.spinics.net/lists/arm-kernel/msg366846.html arch/arm/mach-exynos/mcpm-exynos.c | 32 ++++++++++++++++-------- arch/arm/mach-exynos/platsmp.c | 12 +++++++++ arch/arm/mach-exynos/suspend.c | 50 ++++++++++++++++++++++++++++++++++---- 3 files changed, 79 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index dc9a764..b0d3c2e 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -30,6 +31,8 @@ #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29) #define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30) +static void __iomem *ns_sram_base_addr; + /* * The common v7_exit_coherency_flush API could not be used because of the * Erratum 799270 workaround. This macro is the same as the common one (in @@ -318,10 +321,26 @@ static const struct of_device_id exynos_dt_mcpm_match[] = { {}, }; +static void exynos_mcpm_setup_entry_point(void) +{ + /* + * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr + * as part of secondary_cpu_start(). Let's redirect it to the + * mcpm_entry_point(). This is done during both secondary boot-up as + * well as system resume. + */ + __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */ + __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */ + __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8); +} + +static struct syscore_ops exynos_mcpm_syscore_ops = { + .resume = exynos_mcpm_setup_entry_point, +}; + static int __init exynos_mcpm_init(void) { struct device_node *node; - void __iomem *ns_sram_base_addr; unsigned int value, i; int ret; @@ -387,16 +406,9 @@ static int __init exynos_mcpm_init(void) pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i)); } - /* - * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr - * as part of secondary_cpu_start(). Let's redirect it to the - * mcpm_entry_point(). - */ - __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */ - __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */ - __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8); + exynos_mcpm_setup_entry_point(); - iounmap(ns_sram_base_addr); + register_syscore_ops(&exynos_mcpm_syscore_ops); return ret; } diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index adb36a8..222aa3c 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -137,6 +137,18 @@ void exynos_cpu_power_down(int cpu) */ void exynos_cpu_power_up(int cpu) { + if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") || + of_machine_is_compatible("samsung,exynos5800"))) { + /* + * Bypass power down for CPU0 during suspend. Check for + * the SYS_PWR_REG value to decide if we are suspending + * the system. + */ + int val = __raw_readl(pmu_base_addr + + EXYNOS5_ARM_CORE0_SYS_PWR_REG); + if (!(val & S5P_CORE_LOCAL_PWR_EN)) + return; + } pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); } diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 773140c..e32a42c 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -72,6 +73,7 @@ struct exynos_pm_data { unsigned int *release_ret_regs; void (*pm_prepare)(void); + void (*pm_resume_prepare)(void); void (*pm_resume)(void); int (*pm_suspend)(void); int (*cpu_suspend)(unsigned long); @@ -172,9 +174,28 @@ static int exynos_cpu_suspend(unsigned long arg) static int exynos5420_cpu_suspend(unsigned long arg) { - exynos_flush_cache_all(); + /* MCPM works with HW CPU identifiers */ + unsigned int mpidr = read_cpuid_mpidr(); + unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE); - return exynos_cpu_do_idle(); + + if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) { + mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); + + /* + * Residency value passed to mcpm_cpu_suspend back-end + * has to be given clear semantics. Set to 0 as a + * temporary value. + */ + mcpm_cpu_suspend(0); + } + + pr_info("Failed to suspend the system\n"); + + /* return value != 0 means failure */ + return 1; } static void exynos_pm_set_wakeup_mask(void) @@ -189,9 +210,6 @@ static void exynos_pm_enter_sleep_mode(void) /* Set value of power down register for sleep mode */ exynos_sys_powerdown_conf(SYS_SLEEP); pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); - - /* ensure at least INFORM0 has the resume address */ - pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); } static void exynos_pm_prepare(void) @@ -206,6 +224,9 @@ static void exynos_pm_prepare(void) pm_data->num_extra_save); exynos_pm_enter_sleep_mode(); + + /* ensure at least INFORM0 has the resume address */ + pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); } static void exynos5420_pm_prepare(void) @@ -230,6 +251,10 @@ static void exynos5420_pm_prepare(void) exynos_pm_enter_sleep_mode(); + /* ensure at least INFORM0 has the resume address */ + if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) + pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0); + tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION); tmp &= ~EXYNOS5_USE_RETENTION; pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); @@ -318,6 +343,12 @@ early_wakeup: pmu_raw_writel(0x0, S5P_INFORM1); } +static void exynos5420_prepare_pm_resume(void) +{ + if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) + WARN_ON(mcpm_cpu_powered_up()); +} + static void exynos5420_pm_resume(void) { unsigned long tmp; @@ -346,6 +377,12 @@ static void exynos5420_pm_resume(void) early_wakeup: + /* Restore the CPU0 low power state register */ + tmp = __raw_readl(pmu_base_addr + + EXYNOS5_ARM_CORE0_SYS_PWR_REG); + pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN, + EXYNOS5_ARM_CORE0_SYS_PWR_REG); + tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); tmp &= ~EXYNOS5420_UFS; pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1); @@ -396,6 +433,8 @@ static int exynos_suspend_enter(suspend_state_t state) if (ret) return ret; + if (pm_data->pm_resume_prepare) + pm_data->pm_resume_prepare(); s3c_pm_restore_uarts(); S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, @@ -453,6 +492,7 @@ static struct exynos_pm_data exynos5420_pm_data = { .wkup_irq = exynos5250_wkup_irq, .wake_disable_mask = (0x7F << 7) | (0x1F << 1), .release_ret_regs = exynos5420_release_ret_regs, + .pm_resume_prepare = exynos5420_prepare_pm_resume, .pm_resume = exynos5420_pm_resume, .pm_suspend = exynos5420_pm_suspend, .pm_prepare = exynos5420_pm_prepare,